Multiplication using Look Up Tables

In the previous tutorials, many techniques are discussed for multiplication operation. An alternative way of computing multiplication is using look up tables. Multiplication using look up tables can be useful where serial multiplication is needed or memory devices are available like in FPGA device. This technique is based on the following popular algebraic equation   …

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Signed Array Multiplier

In the previous tutorials, a scheme of Unsigned Array Multiplier is discussed. Unsigned Array Multiplier may be useful when we are concerned only about unsigned numbers. But in majority of digital systems, operands can be signed or unsigned and thus a dedicated signed array multiplier is needed. This signed array multiplier can perform multiplication for …

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Sorting Processor Design to Sort a Serial Stream

Till now the sorting architectures discussed are based on the accessing of data elements in parallel. In real time situation the data streams are serial and serial to parallel conversion is costly as well as time consuming. On the other hand, parallel sorting architectures are very costly in terms of comparators. Thus alternate sorting architectures …

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Clock Division by Non-Integers

Previously we have discussed clock division by odd and even numbers in the tutorial sequential circuits. Later we have also developed a programmable clock divider that divides clock frequency by any integer from 1 to 15. This tutorial talks about clock division by non-integers which is also required is some critical digital systems. Clock division …

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Placement and Routing for ASIC

The previous tutorials [Tutorial 1, Tutorial 2] are on the simulation and synthesis of Verilog files. In addition to these we have also performed linting, code coverage, logic equivalence check, DFT, ATPG, power analysis and Timing analysis using CADENCE and SYNOPSYS tools. Till now we have not discussed anything about the step Placement and Routing …

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Synopsys Simulation and Synthesis ATPG for Combinational Circuits ATPG for Sequential circuits Power Analysis using Synopsys 00

Static Timing Analysis using Cadence Tempus

In the previous tutorials, we have discussed how to simulate or synthesize a design using Synopsys or Cadence. Static Timing Analysis is a very important step in designing an digital design for ASIC. This tutorial is on performing Static Timing Analysis using Cadence Tempus. 1. Open the terminal 2.   Source the cadence.cshrc 3.   In this …

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Power Analysis using Synopsys

In the previous tutorials, simulation and synthesis of digital circuits are described. This tutorial is on Power Analysis using Synopsys. Here, dynamic power consumption of a sequential circuit is estimated. 1.   Open the terminal 2.   Source the synopsys.cshrc 3.   In this experiment, we perform power analysis (dynamic power) of the design using power compiler. 4.  …

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