In the previous tutorials, many techniques are discussed for multiplication operation. An alternative way of computing multiplication is using look up tables. Multiplication using look up tables can be useful where serial multiplication is needed or memory devices are available like in FPGA device. This technique is based on the following popular algebraic equation …
In the previous tutorials, a scheme of Unsigned Array Multiplier is discussed. Unsigned Array Multiplier may be useful when we are concerned only about unsigned numbers. But in majority of digital systems, operands can be signed or unsigned and thus a dedicated signed array multiplier is needed. This signed array multiplier can perform multiplication for …
Till now the sorting architectures discussed are based on the accessing of data elements in parallel. In real time situation the data streams are serial and serial to parallel conversion is costly as well as time consuming. On the other hand, parallel sorting architectures are very costly in terms of comparators. Thus alternate sorting architectures …
Sorting Processor Design to Sort a Serial Stream Read More »
In this tutorial, we will discuss FPGA implementation of a Median filter which is used for removing noises from an image. Noises in an image can be of various types like salt and pepper noise, Gaussian noise, periodic noise etc [1]. Out of these noises, salt and pepper noise is a very basic type of …
FPGA Implementation Median Filter for De-Noising Read More »
Previously we have discussed clock division by odd and even numbers in the tutorial sequential circuits. Later we have also developed a programmable clock divider that divides clock frequency by any integer from 1 to 15. This tutorial talks about clock division by non-integers which is also required is some critical digital systems. Clock division …
In the previous tutorials, we have seen how to use Cadence INNOVUS GUI for placement and routing. But INNOVUS tool works better when used with scripts. It is convenient to use the script based placement and routing as numerous runs are needed to successfully verify an IC. This is also the industrial practice. In this …
In the previous three tutorials, we have learned how prepare the files which are needed to start the placement and routing using INNOVUS. In this tutorial, a basic tutorial on how to perform placement and routing using INNOVUS is given. This is a very fundamental and only covers the basic ideas and follows the tutorial …
In the previous tutorial on Placement And Routing For ASIC, we have seen that one I/O file is also important. This tutorial is on I/O file setup for PnR using INNOVUS. An I/O file is for custom arrangement of I/O pins and I/O pads. This file is optional if the final sign-off analysis is not …
This is a difficult time for everyone now due to the COVID-19 pandemic. The disease COVID-19 is due to the novel CORONA Virus which highly contagious. There is a world wide search is going on for right vaccine. Till the discovery of the right Vaccine the only way to fight against COVID-19 is to wear …
Touch Free Automatic Hand Sanitizer Dispenser Machine Read More »
In the previous tutorial on Placement and Routing using INNOVUS, we have seen how to open the tool and how to import all the files. In this tutorial, we will discuss how to prepare view definition file by performing Multi Mode Multi Corner (MMMC) analysis. MMMC analysis is very important to perform, so that the …
In the previous tutorial, we have presented a basic tutorial on Placement and Routing for ASIC. This tutorial is the first step towards Placement and Routing using INNOVUS tool. We will cover very basics of Placement and Routing using INNOVUS as it is a huge area and many tutorials are available on internet. Here, we …
The previous tutorials [Tutorial 1, Tutorial 2] are on the simulation and synthesis of Verilog files. In addition to these we have also performed linting, code coverage, logic equivalence check, DFT, ATPG, power analysis and Timing analysis using CADENCE and SYNOPSYS tools. Till now we have not discussed anything about the step Placement and Routing …
Synopsys Simulation and Synthesis ATPG for Combinational Circuits ATPG for Sequential circuits Power Analysis using Synopsys 00
In the previous tutorials, we have discussed how to simulate or synthesize a design using Synopsys or Cadence. Static Timing Analysis is a very important step in designing an digital design for ASIC. This tutorial is on performing Static Timing Analysis using Cadence Tempus. 1. Open the terminal 2. Source the cadence.cshrc 3. In this …
In the previous tutorials, simulation and synthesis of digital circuits are described. This tutorial is on Power Analysis using Synopsys. Here, dynamic power consumption of a sequential circuit is estimated. 1. Open the terminal 2. Source the synopsys.cshrc 3. In this experiment, we perform power analysis (dynamic power) of the design using power compiler. 4. …
