Power Analysis using Synopsys

In the previous tutorials, simulation and synthesis of digital circuits are described. This tutorial is on Power Analysis using Synopsys. Here, dynamic power consumption of a sequential circuit is estimated. 1.   Open the terminal 2.   Source the synopsys.cshrc 3.   In this experiment, we perform power analysis (dynamic power) of the design using power compiler. 4. 

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Linting is a process of running a program that will analysis the code for potential errors. This tutorial is for checking errors and warnings in a Verilog code using Cadence tool. Open the terminal Source the cadence.cshrc In a new ASIC lab directory, write a Verilog coded design (in this example fifo.v) Write the linting

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