ASIC LAB

Power Analysis using Synopsys

In the previous tutorials, simulation and synthesis of digital circuits are described. This tutorial is on Power Analysis using Synopsys. Here, dynamic power consumption of a sequential circuit is estimated. 1.   Open the terminal 2.   Source the synopsys.cshrc 3.   In this experiment, we perform power analysis (dynamic power) of the design using power compiler. 4.  …

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Synopsys Simulation and Synthesis

Here, tutorial on simulation of Verilog file using Synopsys EDA tool is given. Also, synthesis using Deign Vision tool is also shown. The reader find this tutorial on Synopsys Simulation and Synthesis very useful. 1.   Open the terminal 2.   Source the synopsys.cshrc 3.   Check whether the commands are working as below. Terminal will echo the …

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GENUS Synthesis using SCRIPTS

In our earlier tutorials [GENUS Synthesis With Constraints, GENUS Synthesis Without Constraints] on synthesis of Verilog files using Cadence Genus tool, we have seen how synthesis can be performed with or without timing constraints. But it is very painful to perform synthesis operation by executing commands one by one in the command prompt. Thus industry …

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Linting

Linting is a process of running a program that will analysis the code for potential errors. This tutorial is for checking errors and warnings in a Verilog code using Cadence tool. Open the terminal Source the cadence.cshrc In a new ASIC lab directory, write a Verilog coded design (in this example fifo.v) Write the linting …

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