Sequential Circuits By SHIRSHENDU ROY | 17th September 2020 0 Comment Welcome to your QUIZ on Sequential Circuits 1 Your Name Please Enter Your Email 1. In a negative edge triggered flip-flop, in order to have the output Q state 0, 0 and 1 in the next three successive clock pulses the J-K input states required would be respectively .00,00 and 1000,01 and 1100,10 and 1101,10 and 112. The initial state of MOD-16 down counter is 0110. After 37 clock pulses, the state of the counter will be.10110110010000013. Symmetrical square wave of time period 100 us can be obtained from square wave of time period 10 us by using adivide by-5 circuitdivide by-2 circuitdivide by-5 circuit followed by divide by-2 circuita JK flip-flop4. T-flip-flop function is obtained from a JK flip-flop. If the flip-flop belongs to TTL family, the connections needed at the input must be.J=K=1J=K=0J=1 and K =0J=0 and K =15. A ring counter consisting of five flip-flops will have5 states10 states32 statesInfinite states6. The 54 / 74164 chip is an 8-bit serial-input-parallel â€“output shift register. The clock is 1 MHz the time needed to shift an 8-bit binary number into chip is1 us2 us8 us16 us7. Minimum number of J-K flip-flops needed to construct a BCD counter is23458. The number of unused states in a 4-bit Johnson counter is248129. For the circuit shown below the counter state (Q1,Q0) follows the sequence00, 01, 10, 11, 00, ..00, 01, 10, 00, 01, ..00, 01, 11, 00, 01, ..00, 10, 11, 00, 10, ..10. Analyse the circuit shown below. Assume initial state is 00, determine what input sequence would lead to state 11?1 - 11 - 00 - 0State 11 is unreachable11. In the following figure 1010 is initially loaded in the register. After how many clock pulses the content of the shift register will be 1010 again.37111512. An X-Y flip-flop, whose characteristic table is given below is to be implemented using J-K flip-flop. This can be done by making\[J=X, K = \bar{Y}\]\[J=\bar{X}, K = Y\]\[J=Y, K = \bar{X}\]\[J=\bar{Y}, K = X\]13. The J-K flip-flop shown below is initially reset, so that Q = 0. If a sequence of four clock pulses is then applied, with the J and K inputs as given in the figure. The resulting sequence of values that appear at the output Q starting with its initial state is given by0101101010001100010114. Which of the following flip-flop is used as a latch?J-K flip-flopR-S flip-flopT flip-flopD flip-flop15. The below circuit illustrates a typical application of the J-K flip-flops. What does this represent.A shift registerA data storage deviceA frequency divider circuitA decoder circuit16. A 1ms pulse can be converted into a 10 ms pulse by using which one of the following?An astable multivibratorA mono stable multivibratorA bistable multivibratorA J-K flip-flop17. The characteristic equation of a J-K flip-flop is\[ Q_{N+1} = J\bar{Q_N} + \bar{K}Q_N \]\[ Q_{N+1} = J+ \bar{K}Q_N \]\[ Q_{N+1} = K\bar{Q_N} + \bar{J}Q_N \]\[ Q_{N+1} = K + \bar{J}Q_N \]18. The circuit shown below is ofMod-5 counterMod-6 counterMod-7 counterMod-8 counter19. 12 MHz clock frequency is applied to a cascaded counter of Mod-3 counter, Mod-4 counter and Mod-5 counter. What is the lowest output frequency and Mod number .200 KHz, 601 MHz, 603 MHz, 124 MHz, 1220. What will be the content of the shift register shown below after 3 clock pulses?000001011010111121. The below shown J-K flip-flop is initially cleared. The output sequence at Q will be after 6 clock pulses01000101100101001001010122. Total number of 1's in a 15-bit shift register is to be counted by clocking into a counter which is preset to 0. The counter must have which one of the following ?4-bits5-bits3-bits16-bits23. Output characteristic of T flip-flop is\[ Q^* = TQ + \bar{T}\bar{Q}\]\[ Q^* = T\bar{Q} + \bar{T}Q\]\[ Q^* = T + Q \]\[ Q^* = T\bar{Q}\]24. In the 3-bit shift register, to have content '000' again the number of clock cycles required would be3681625. What is the maximum modulus number for a counter with 5 number of flip-flops ?163264826. Number of flip-flops required to construct mod-10 counter will be123427. Number of flip-flops required to divide input frequency by 64?245628. How many illegitimate states a synchronous mod-6 counter has ?321029. R-S latch is aCombinational circuitSynchronous sequential Element1 bit memory element1 clock delay element30. A 0 to 6 counter consists of 3 flip-flops and a combination circuit of 2 input gates. The combination circuit consists ofone AND gateone OR gateone AND gate and one OR gatetwo AND gates31. What will be the status of (Q1,Q0) after 3 clock cycles if the flip-flops are initially cleared.1001001132. The Race Around condition exists in J-K flip-flop whenJ=0, K=1J=1, K=0J=0, K=0J=0, K=133. In a J-K flip-flop, the output Q is 1 and it does not change when a clock pulse is applied. The possible condition of J and K will be. (x is don't care)x and 0x and 10 and x1 and x34. What type of counter is shown hereSyhnchronousJohnsonRingNone35. Which of the following is not a characteristic of a flip-flop?The flip-flop is a bistable device with only two stable statesThe flip-flip has two input signalsThe flip-flip has two output signalsThe outputs are complement of each other36. which of the following statements is not correct ?A flip-flop is used to store 1-bit information.Race-around condition occurs in J-K flip-flop to store 2-bits of information.Master-Slave configuration is used in flip-flops to store 2-bits of informationA transparent latch consists of a D-type flip-flop.37. Which type of flip-flop is realized in the following figure ?SR flip-flopJ-K flip-flopT flip-flopD flip-flop38. If input frequency is 12 MHz then the output frequency is24 KHz12 KHz6 KHz3 KHzPlease fill in the comment box below. Time is Up! Time's up (Visited 128 times, 1 visits today)00