FPGA Implementation of XOR Function using ANN

Artificial Neural Networks (ANN) are very popular to realize different critical functions related to any field of study. In this project, a simple exclusive-OR function is realized with the help of ANN. The purpose of the XOR function is to perform XOR operation between two inputs which can take value anything within the range -1 to 1. The output will be binary based on the values of the inputs. The ANN logic is explained here and finally, FPGA implementation of XOR function using ANN is demonstrated in this tutorial.

Three-level ANN architecture is used here. In the input level, there are two nodes named as I_1 and I_2. In the hidden layer also we have two nodes named as H_1 and H_2. At the output, we have only one node named as O_1. The architecture is shown below.

Figure 1: ANN architecture to realize XOR function.

The input nodes follow the logic that is given below

(1)   \begin{equation*} b =  \begin{cases}     1,& \text{if } |x|\geq 0.5\\     0,              & \text{otherwise} \end{cases} \end{equation*}

The logic of the Hidden layer nodes is given below.

(2)   \begin{equation*} a_1 =  \begin{cases}     1,& \text{if } b_1 + b_2 \geq 1\\     0,              & \text{otherwise} \end{cases} \end{equation*}

(3)   \begin{equation*} a_2 =  \begin{cases}     1,& \text{if } -b_1 - b_2 \geq -1\\     0,              & \text{otherwise} \end{cases} \end{equation*}

Finally, the logic at the output node is given below.

(4)   \begin{equation*} y =  \begin{cases}     1,& \text{if } a_1 + a_2 \geq 2\\     0,              & \text{otherwise} \end{cases} \end{equation*}

The ANN structure to realize the XOR function is implemented using the basic digital blocks and finally implemented on FPGA device. Fixed point arithmetic with the help of two’s complement representation is used here. The data width of 12 bits is used to represent the input data x where 10 bits are used for the fractional part. The digital hardware for the input nodes is shown below.

Figure 2: Architecture for Input Nodes

MSB of the input signal is used to perform either addition or subtraction before the comparator block. One input of the comparator is connected to 0.5 constantly. A 12-bit unsigned comparator is used here. The final and overall architecture is shown below

Figure 3: Overall Implementation of XOR function using ANN

The architecture is very simple and self-explanatory. The overall architecture is implemented and verified using xc7a35tcpg236-2 FPGA. Simulation is done using the Xilinx-Vivado tool. The simulation result for the XOR implementation problem is shown below.

Figure 4: XILINX Simulation

The hardware utilization report with respect to the targetted FPGA is shown below

Figure 5: Hardware Summary
Figure 6: Hardware Utilization Summary

This project was completed by the following students who are students of Dayandanda Sagar University.

  • SHASHANK R
  • SOURAV D
  • SANKETH KUMAR
  • PRITHIVRAJ Mulge
Verilog code for XOR using ANN (643 downloads )
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