Tag Archives: Synthesis

ASIC Tutorials I

Here, we will discuss the tutorials on how to synthesize a Verilog code starting from simulation, syntax checking, code coverage using CADENCE EDA tool. Basic Simulation on CADENCE Linting Code Coverage Logic Equivalence Check Genus Synthesis without Constraints Genus Synthesis with Constraints Genus Synthesis using Scripts Static Timing Analysis using Cadence Tempus +10

FPGA Implementation

In this Tutorial, a detailed discussion on FPGA implementation of complex digital circuits is discussed. First, a brief overview on FPGA is given then the steps involved in implementing a circuit are illustrated. Specific examples are shown to illustrate the steps. FPGA: Basic Overview. A tutorial on FPGA Implementation using XILINX ISE. Estimation of Dynamic… Read More »


In this part, a tutorial on the FPGA implementation of digital systems is discussed. A simplified version of FPGA based design flow is given in the following diagram. Lets consider an example to illustrate the FPGA implementation procedure. The circuit shown in Fig. 2 is considered as a test circuit. Design Entry There are different… Read More »