Category Archives: ASIC

Placement and Routing for ASIC

The previous tutorials [Tutorial 1, Tutorial 2] are on the simulation and synthesis of Verilog files. In addition to these we have also performed linting, code coverage, logic equivalence check, DFT, ATPG, power analysis and Timing analysis using CADENCE and SYNOPSYS tools. Till now we have not discussed anything about the step Placement and Routing… Read More »

ASIC Tutorials I

Here, we will discuss the tutorials on how to synthesize a Verilog code starting from simulation, syntax checking, code coverage using CADENCE EDA tool. Basic Simulation on CADENCE Linting Code Coverage Logic Equivalence Check Genus Synthesis without Constraints Genus Synthesis with Constraints Genus Synthesis using Scripts Static Timing Analysis using Cadence Tempus +10