FPGA Implementation Median Filter for De-Noising

By | 11th February 2021

In this tutorial, we will discuss FPGA implementation of a Median filter which is used for removing noises from an image. Noises in an image can be of various types like salt and pepper noise, Gaussian noise, periodic noise etc [1]. Out of these noises, salt and pepper noise is a very basic type of noise which can appear in any image. Salt and pepper noise can be easily characterized and removed in spatial domain.

Median Filter

Various type of spatial filters are proposed in literature to remove salt and pepper noise. Median filter is a very common and popular filter for image denoising. There are many variation of Median filter but here we will discuss the basic Median filter. The operating principle of a basic Median filter is based on replacing the pixel on which the window is operated by Median value of all the pixels inside that window. The image denoising using the Median filter for simple Grey scale image is shown in Figure 1.

In Grey scale image pixels values are ranging from 0 to 255. Thus in a salt and pepper noise affected image, noisy pixel value can be either very close to 255 or as small as 0. The Median filter works based on the sliding window operation. A W\times W window can be set as 3\times 3, 5\times 5 or 7\times 7 for an n\times n image and in a window their are W^2 pixels. The sliding window operation is shown in Figure 2 for a simple 4\times 4 image. Here there are four rows of pixels. In the first step, Row 1 to Row 3 are operated and (x_2,y_2) is the center pixel on which the 3\times 3 window is operated. Then the window slides to the right and (x_3,y_3) become the center pixel. Once the window slides to the extreme right then another Row takes part in the denoising operation. For example here in the second step, Row 2 to Row 4 are operated. Denoising operation can not be done on the boundary pixels.

Figure 2: Window operation for 4\times 4 image.

FPGA Implementation of Median Filter

A simple architecture of the Median filter is shown in Figure 3. In FPGA implementation of median filter, there are three major steps which are Sliding window operation, Filtering operation and Filtered image restoration. The image acquisition is also an important operation which is achieved here by placing a dual port Input RAM of size N\times N \times 8. A simple up counter is used here to write the pixels in the RAM block. Simultaneously the pixels can be read from the Input RAM block and fed to a block which does window operation. This block feds all the pixels in a window to the Median computation block. The Median value is then replaced in the original image in the restoration phase.

Figure 3: A possible architecture of the Spatial Median Filter

Here, 3\times 3 window is chosen for image denoising. A simple scheme for sliding window operation reported in [2] is shown in Figure 4. Here, two line buffers are used and size of each is N\times 8. Initially, Row 1 is written to the Line buffer 1 through the DeMUX and in this time phI signal is high. Then Row 2 is written to the Line buffer 2 when the phII signal is high. The phI and phII signals are opposite and non-overlapping to each other. Now, Line buffer 1 has Row 1 and Line buffer 2 has Row 2. Row 3 is now read from the input RAM and at the same time both the buffers are also read. Simultaneously, Row 3 is also written to the Line buffer 1. Three clock cycles are needed to form the 3\times 3 window using the nine registers.

Figure 4: A scheme for 3\times 3 window operation.

Various architectures are also reported to find Median efficiently. The Median computation block reported in [3] is adopted here and is shown in Figure 5. This parallel architecture uses total 19 BN blocks. The structure of the BN block is already discussed in the previous tutorial for sorting. Here, pipeline registers are inserted to improve the timing performance. It is certain that increasing the value of W will increase the number of BN blocks.

Figure 5: An architecture for computing median out of 8 data elements.
Figure 6: An architecture for the restoration counter.

In the image restoration phase, noisy pixels are replaced with the corrected one. This restoration can be done on the input image also. But here a separate output RAM is used. Note that in order to retain the boundary pixels, the output RAM should initially contain the boundary pixels. A restoration counter write the Median values in the output RAM at their exact location. If the size of the image is 16\times 16 then the restoration counter will count as

17\hspace{2pt}18\hspace{2pt}19....30\hspace{2pt}33\hspace{2pt}34\hspace{2pt}35....46\hspace{2pt}49....

A possible scheme of the restoration counter is shown in the Figure 6. Two loadable counters are used, one is of 8-bit and another is of 4-bit. The 4-bit counter is used to load the 8-bit counter with the load values (d) as 17, 33, 49, ..... Initially the start signal loads the 8-bit counter with d=17. Then both the counter starts counting. The 4-bit counter counts upto 13 and generate tc1 signal which again loads the 8-bit counter with next load value. Both the counters have a common enable input. This way the restoration counter works.

References

  1. R.C.Gonzalez and R. Woods, Digital Image Processing. Prentice Hall,
    2007.
  2. P.-Y. Chen, C.-Y. Lien, and H.-M. Chuang, “A low-cost vlsi implementation for efficient removal of impulse noise,” Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol. 18, no. 3, pp. 473–481, 2010.
  3. J.L.Smith, “Implementing median filters in xc4000e fpgas,” in Proc. of VII, 1996, p. 16.
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