Signal processing algorithms sometimes involve computation of exponential as well as logarithm. Thus it is important to implement both the functions on digital hardware. In our previous tutorials, we have discussed implementation of exponential function. In this work, design of digital hardware to find logarithm of a number is discussed. The logarithm function is computed […]
Implementation of Logarithm Function Read More »
In the previous post, we have discussed the theory for computation of exponential and discussed about its hardware architecture. In this post, we will discuss an alternative architecture to compute the exponential. If we examine the equations which evaluate the exponential function, then we can see that is multiplied by or . In the previous
Efficient Architecture for Exponential Read More »
Signal processing algorithms sometimes involve computation of exponential. Thus it is important to implement the exponential function. In this work, design of digital hardware for exponential function is discussed. Like other elementary functions, exponential function is also computed using the iterative formulas. In this work, computation of the exponential function is shown for three cases.
Computation of Exponential Function Read More »
I. Introduction Fast Fourier transform (FFT), an efficient technique to perform discrete Fourier transform (DFT), is the most important block in the signal processing domain. FFT is used to convert a signal in time domain to its frequency domain. On the other hand, inverse FFT (IFFT) block is used to convert the signal in frequency
FPGA Implementation of 1024-point FFT/IFFT Processor Read More »
Fast Fourier Transform (FFT) is an efficient technique to implement Discrete Fourier Transform (DFT). FFT is used to observe the frequency domain characteristics of a signal or an image. Similarly Inverse FFT (IFFT) is used to convert a frequency domain signal to its time domain. Thus FFT and IFFT are very important functions in the
MATLAB Realization of FFT/IFFT w/o Direct Function Read More »
State Partition Method for State Minimization is also powerful as the Implication Chart Method and better than Row Equivalence method. In this technique, the states are partitioned into groups based on the possibility that they can be combined. Lets consider the example state table as shown in Table 1 for state minimization using state partition
State Partition Method for State Minimization Read More »
Implication Chart Method for State Minimization is very popular for reducing the steps of an FSM and it is more machine friendly method than Row Equivalence Technique. In this method, a chart is prepared to find the equivalent steps. The implication chart is shown in Figure 1. States are written along the x-axis as ,
Implication Chart Method for State Minimization Read More »
Row Equivalence Method for State Minimization is a very simple technique to reduce number of states of an FSM. In the row equivalence method, it is checked that rows of a state table are equivalent or not. Here, a comparatively strict definition of state equivalence is used. The conditions for two states and to be
Row Equivalence Method for State Minimization Read More »
In the previous post FSM Design, we have discussed design of Mealy and Moore state machines using Verilog. State minimization is important if we want to reduce number of states in a complex FSM which has many redundant states. If the number of states are reduced then number of bits required for state assignment will
State Minimization Techniques for FSM Read More »
In the previous tutorials, many techniques are discussed for multiplication operation. An alternative way of computing multiplication is using look up tables. Multiplication using look up tables can be useful where serial multiplication is needed or memory devices are available like in FPGA device. This technique is based on the following popular algebraic equation
Multiplication using Look Up Tables Read More »
In the previous tutorials, a scheme of Unsigned Array Multiplier is discussed. Unsigned Array Multiplier may be useful when we are concerned only about unsigned numbers. But in majority of digital systems, operands can be signed or unsigned and thus a dedicated signed array multiplier is needed. This signed array multiplier can perform multiplication for
Signed Array Multiplier Read More »
Till now the sorting architectures discussed are based on the accessing of data elements in parallel. In real time situation the data streams are serial and serial to parallel conversion is costly as well as time consuming. On the other hand, parallel sorting architectures are very costly in terms of comparators. Thus alternate sorting architectures
Sorting Processor Design to Sort a Serial Stream Read More »
In this tutorial, we will discuss FPGA implementation of a Median filter which is used for removing noises from an image. Noises in an image can be of various types like salt and pepper noise, Gaussian noise, periodic noise etc [1]. Out of these noises, salt and pepper noise is a very basic type of
FPGA Implementation Median Filter for De-Noising Read More »
Previously we have discussed clock division by odd and even numbers in the tutorial sequential circuits. Later we have also developed a programmable clock divider that divides clock frequency by any integer from 1 to 15. This tutorial talks about clock division by non-integers which is also required is some critical digital systems. Clock division
Clock Division by Non-Integers Read More »
In the previous tutorials, we have seen how to use Cadence INNOVUS GUI for placement and routing. But INNOVUS tool works better when used with scripts. It is convenient to use the script based placement and routing as numerous runs are needed to successfully verify an IC. This is also the industrial practice. In this
PnR using INNOVUS with scripts Read More »
