I/O file setup for PnR using INNOVUS

In the previous tutorial on Placement And Routing For ASIC, we have seen that one I/O file is also important.  This tutorial is on I/O file setup for PnR using INNOVUS.  An I/O file is for custom arrangement of I/O pins and I/O pads. This file is optional if the final sign-off analysis is not […]

MMMC file setup for PnR using INNOVUS

In the previous tutorial on Placement and Routing using INNOVUS, we have seen how to open the tool and how to import all the files. In this tutorial, we will discuss how to prepare view definition file by performing Multi Mode Multi Corner (MMMC) analysis. MMMC analysis is very important to perform, so that the […]

Importing Files for PnR using INNOVUS

In the previous tutorial, we have presented a basic tutorial on Placement and Routing for ASIC. This tutorial is the first step towards Placement and Routing using INNOVUS tool. We will cover very basics of Placement and Routing using INNOVUS as it is a huge area and many tutorials are available on internet. Here, we […]

Placement and Routing for ASIC

The previous tutorials [Tutorial 1, Tutorial 2] are on the simulation and synthesis of Verilog files. In addition to these we have also performed linting, code coverage, logic equivalence check, DFT, ATPG, power analysis and Timing analysis using CADENCE and SYNOPSYS tools. Till now we have not discussed anything about the step Placement and Routing […]

ATPG for Combinational Circuits

Automatic Test Pattern Generation and Automatic Test Pattern Generator (ATPGA) is an electronic design automation method/technology used to find an input (or test) sequence that, when applied to a digital circuit, enables automatic test equipment to distinguish between the correct circuit behavior and the faulty circuit behavior caused by defects. This tutorial focuses on ATPG for combinational circuits using Synopsys Tetramax tool. 1.   Open the terminal 2.   Source […]

Synopsys Simulation and Synthesis

Here, tutorial on simulation of Verilog file using Synopsys EDA tool is given. Also, synthesis using Deign Vision tool is also shown. The reader find this tutorial on Synopsys Simulation and Synthesis very useful. 1.   Open the terminal 2.   Source the synopsys.cshrc 3.   Check whether the commands are working as below. Terminal will echo the […]

ASIC Tutorials I

Here, we will discuss the tutorials on how to synthesize a Verilog code starting from simulation, syntax checking, code coverage using CADENCE EDA tool. Basic Simulation on CADENCE Linting Code Coverage Logic Equivalence Check Genus Synthesis without Constraints Genus Synthesis with Constraints Genus Synthesis using Scripts Static Timing Analysis using Cadence Tempus 00

GENUS Synthesis using SCRIPTS

In our earlier tutorials [GENUS Synthesis With Constraints, GENUS Synthesis Without Constraints] on synthesis of Verilog files using Cadence Genus tool, we have seen how synthesis can be performed with or without timing constraints. But it is very painful to perform synthesis operation by executing commands one by one in the command prompt. Thus industry […]