The basic building blocks of digital systems are explained in the previous tutorials. In this tutorial section, we will go through designing the complex architectures. We will start by implementing the basic designs and then we will implement more complex designs. Concurrently we will evaluate the performance of the designs in terms of timing, hardware and power.
- FPGA Implementation of Frequency Domain Denoising Filters:– In this post, we have presented some novel architectures for FPGA based removal of periodic noise. A survey of different image noises is also given. Two type of frequency domain filters, viz., mean and median filters are implemented in this post. Though the architectures are implemented on the basic SPARTAN 3E starter kit, readers can gain some important concepts on implementing image processing algorithms and on frequency domain filtering.
- FPGA Implementation of DIT Based 8-Point FFT:- This is an example project to demonstrate how to design complex circuits. This design may not be directly useful but the basic concepts will help to design other circuits. Structural implementation is followed with moderate optimization. Design is targeted to SPARTAN 3E device and design performance is estimated.
- FPGA Implementation of K-means Algorithm:- In this work, a novel architecture of K-means algorithm is presented. A prototype of the K-means algorithm is implemented here on NEXYS DDR2 FPGA device. Though the architecture is implemented for smaller value of K, can be adopted for higher value K also. The complete analysis of the design is given here. All the Verilog code, Matlab code and the example of the design is given here.
- Parallel FPGA Implementation FIR Filters: In this work, parallel FPGA implementation of FIR filters is demonstrated. A low pass filter is designed using different structures. All the structures are implemented on the NEXYS DDR2 FPGA device. The performances of all the structures are compared. All the Verilog and MATLAB codes are attached with this work.
- Parallel and Pipeline FPGA Implementation of IIR Filters: In this work, parallel and pipeline FPGA implementation of IIR filters is demonstrated. A low pass filter is designed using different structures. All the structures are implemented on the NEXYS DDR2 FPGA device. The performances of all the structures are compared. All the Verilog and MATLAB codes are attached with this work.
- FPGA Implementation Median Filter for De-Noising: In this tutorial, a median filter is implemented on FPGA to remove noises from an image. Basic salt and pepper noise is considered here.
- FPGA Implementation of 1024-point FFT/IFFT Processor: In this tutorial, a parallel and pipelined architecture of 1024-FFT/IFFT processor is presented. This architecture is based on radix-2 DIF algorithm based. Also this architecture is based on Twiddle factor storage. The novelty of this architecture is that it uses less storage to store twiddle factors.