# Fast multiplication

## Signed Array Multiplier

In the previous tutorials, a scheme of Unsigned Array Multiplier is discussed. Unsigned Array Multiplier may be useful when we are concerned only about unsigned numbers. But in majority of digital systems, operands can be signed or unsigned and thus a dedicated signed array multiplier is needed. This signed array multiplier can perform multiplication for […]

## Synopsys Simulation and Synthesis

Here, tutorial on simulation of Verilog file using Synopsys EDA tool is given. Also, synthesis using Deign Vision tool is also shown. The reader find this tutorial on Synopsys Simulation and Synthesis very useful. 1.   Open the terminal 2.   Source the synopsys.cshrc 3.   Check whether the commands are working as below. Terminal will echo the

## Fast Multiplication

The fast multiplication can be achieved in three general ways. The sequential multipliers sequentially generates the partial products and adds them with the previously stored partial products. In the second method, high speed parallel multipliers generate the partial products in parallel and adds them by a fast multi-operand adder. The third method corresponds to use

## Dedicated Square Block

In the previous tutorials, we have discussed techniques which can be used to achieve fast multiplication. But when the multiplicand and the multiplier are same, there must be some way to simplify the implementation. Thus squaring operation does not require the full length hardware of a multiplier. In applications where a squaring operation is required,

## Booth’s Array Multiplier

Booth’s algorithm is a powerful technique to achieve fast multiplication. Booth’s algorithm can be employed either sequentially or with the help of fast addition methods or in the form of array multiplication. In this tutorial, Booth’s Radix-4 algorithm is used to form an architecture to multiply two 6-bit numbers in the form of array multiplier.

## Alternative Techniques for Partial Product Accumulation

Several techniques are suggested for partial products accumulation. Some of them targets to reduce the logic elements to reduce hardware complexity whereas some of them targets to reduce numbers of levels in the tree of partial products to achieve high speed. As the number of levels increases irregularity in the design also increases. The irregularities

## Accumulation of Partial Products for Signed Numbers

Earlier we have discussed how the partial products for a unsigned multiplier can be accumulated using suitable organization and consuming minimum number of counters. In this section, accumulation will be done by considering negative partial products. If some of the partial products are negative numbers represented in two’s complement number system, then matrix of bits

## Implementing Large Multiplier Using Smaller ones

Like Booth’s multiplication algorithm another method reduction of partial products is implementing higher multipliers by smaller ones. The larger multiplier blocks can be realized using smaller multiplier blocks. A multiplier can be realized using four multiplier blocks. This is based on the following equation where is the most significant halve of A, is the most

## Booth’s Multiplication Algorithm

Booth’s multiplication algorithm is based on the fact that fewer partial products are needed to be generated for consecutive ones and zeros. For consecutive zeros, a multiplier only needs to shift the accumulated result to the right without generating any partial products. For example, the accumulated result is shifted one bit right for every ‘0’