Tag Archives: Cadence tutorial

Placement and Routing using INNOVUS

In the previous three tutorials, we have learned how prepare the files which are needed to start the placement and routing using INNOVUS. In this tutorial, a basic tutorial on how to perform placement and routing using INNOVUS is given. This is a very fundamental and only covers the basic ideas and follows the tutorial… Read More »

MMMC file setup for PnR using INNOVUS

In the previous tutorial on Placement and Routing using INNOVUS, we have seen how to open the tool and how to import all the files. In this tutorial, we will discuss how to prepare view definition file by performing Multi Mode Multi Corner (MMMC) analysis. MMMC analysis is very important to perform, so that the… Read More »

Importing Files for PnR using INNOVUS

In the previous tutorial, we have presented a basic tutorial on Placement and Routing for ASIC. This tutorial is the first step towards Placement and Routing using INNOVUS tool. We will cover very basics of Placement and Routing using INNOVUS as it is a huge area and many tutorials are available on internet. Here, we… Read More »

Placement and Routing for ASIC

The previous tutorials [Tutorial 1, Tutorial 2] are on the simulation and synthesis of Verilog files. In addition to these we have also performed linting, code coverage, logic equivalence check, DFT, ATPG, power analysis and Timing analysis using CADENCE and SYNOPSYS tools. Till now we have not discussed anything about the step Placement and Routing… Read More »

GENUS Synthesis using SCRIPTS

In our earlier tutorials [GENUS Synthesis With Constraints, GENUS Synthesis Without Constraints] on synthesis of Verilog files using Cadence Genus tool, we have seen how synthesis can be performed with or without timing constraints. But it is very painful to perform synthesis operation by executing commands one by one in the command prompt. Thus industry… Read More »

GENUS Synthesis With Constraints

This tutorial is in continuation with our previous tutorial on Genus Synthesis Without Constraints (Timing Constraints). The timing constraints are written in Synopsys Design Constraint (SDC) file. 1. Open the terminal and type csh 2. Source the cadence.cshrc. 3. In ASIC lab folder, make a new directory. In this, make design.v (in this example counter.v).… Read More »

Linting

Linting is a process of running a program that will analysis the code for potential errors. This tutorial is for checking errors and warnings in a Verilog code using Cadence tool. Open the terminal Source the cadence.cshrc In a new ASIC lab directory, write a Verilog coded design (in this example fifo.v) Write the linting… Read More »