Combinational Circuits 1 By SHIRSHENDU ROY | 25th August 2020 0 Comment Welcome to your QUIZ on Combinational Circuits 1 Your Name Please Enter Your Email 1. What is a majority voter circuit?Output is one when above 50 % inputs are falseOutput is one when above 50 % inputs are trueOutput is one when 50 % inputs are trueNone of the above2. Karnaugh map is used tominimize the number of flip-flops in a digital circuitminimize the number of gates in a digital circuitminimize the number of gates and fan-in of a digital circuitdesign gates3. Which one of the following can be used as parallel to serial converter?DecoderDigital countermultiplexerDemultiplexer4. Which one of the following statements correctly defines the full–adder?a circuit having two inputs used to add two binary digits. It produces their sum and carry as output.a circuit having three inputs used to add two binary digits plus a carry. It produces their sum and carry as outputs.a circuit used in the least significant position when adding two binary digits with no carry into consider. It produces there sum and carry as outputs.a circuit having two inputs and two outputs5. Which statements are not true regarding a multiplexer?Selects one of the several inputs and transmits it to a single output.Routes the data from a single input to one of many outputConverts the parallel data to serial dataIs a combinational circuit6. If the output of logic gate is ‘1’ when all its inputs are at logic ‘0’, the gate is eithera NAND or EX-OR gatea NOR or an EX-NOR gatean OR or an EX-NOR gatea AND or an EX-OR gate7. The number of a 4-line-to-16-line decoders required to make an 8-line-to-256-line decoder is161732648. Four memory chip of 16x4 size have their address busses connected together. This system will be of size.64x416x1632x8256x19. With 4 Booleans variables, how many Booleans expressions can be formed?162561024 (1 K)64 K (64x1024)10. Which one of the following statements is correct?PROM contains a programmable ‘AND’ array and a fixed ‘OR’ arrayPLA contains a fixed ‘AND’ array and a programmable ‘OR’ arrayPROM contains a programmable ‘OR’ array and fixed ‘AND’ arrayPLA contains a programmable ‘AND’ array and programmable ‘NOR’ array11. Which one of the statements describes the operations of multiplexer?A logic circuit used to generate a coded outputA logic circuit used to generate F’s complementA logic circuit that accepts two or more inputs and allows one of them at a time to get through the output.A logic circuits that transmits one input to several output lines.12. A ROM is used to implement a ‘squarer”, which outputs the square of a 4-bit number. What must be size of ROM?16 address lines and 16 data lines4 address lines and eight data lines8 address lines and eight data lines4 address lines and 16 data lines13. What is the minimum number of NAND gates required to implement \[A + A\bar{B} + A\bar{B}C ?\]014714. The output of a two level AND-OR gate network is F. What is the output when all the gates were replaced by NOR gates?FComplement of FDual of FDual of Complement of F15. The output of a two level AND-OR gate network is F. What is the output when all the gates were replaced by NAND gates?FComplement of FDual of FDual of Complement of F16. Assume that only x and y logic inputs are available, and their complements are not available. What is the minimum number of 2-inputs NAND gates required to implement \[A\oplus B\hspace{2pt} ?\]234517. A ROM is used to store the table for multiplication of two 8-bit unsigned integer. The size of the ROM required is256 X 164 k X 84 k X 1664 k X 1618. In NOR-NOR configuration, the minimum number of NOR gates needed to implement the function \[X + X\bar{Y} + X\bar{Y}Z \hspace{2pt}\text{is}\]532019. Output y of the given circuit is10xComplement of x20. The logic circuit realized by the circuit shown below isB Ex-NOR CB Ex-OR CA Ex-NOR CA Ex-OR C21. Minimized logic expression of the circuit shown below is\[ \overline{A.\bar{B}.C}\]\[ \overline{\bar{A}.B.\bar{C}}\]\[ \overline{A.B.C}\]\[ \bar{A}.B.\bar{C}\]22. The circuit shown below realizes the function\[ (\overline{A + B} + C)(\bar{D}\bar{E})\]\[ (\overline{A + B} + C)(D\bar{E})\]\[ (A + \overline{B + C})(\bar{D}E)\]\[ (A + B + \bar{C})(\bar{D}\bar{E})\]23. The logic operations of two combinational circuits shown below areEntirely differentIdenticalComplementaryDual24. The half adder circuit in the given figure has inputs AB = 11. The outputs will beX = 0 and Y = 0X = 0 and Y = 1X = 1 and Y = 0X = 1 and Y = 125. The circuit shown below isan adder circuita subtractor circuita comparator circuita parity generator circuit26. The following circuit is functionally equivalent toNOR gateOR gateEX-OR gateNAND gate27. What is the required input condition (A, B, C) to make the output X=1 for the below shown circuit(1,0,1)(0,0,1)(1,1,1)(0,1,1)28. What is the expression of the Y for the following circuit\[ \overline{(C + D)\oplus (A\oplus B)}\]\[ A \oplus B\]\[ \overline{A \oplus B}\]\[ \overline{C \oplus B \oplus A}\]29. Which logic function is implemented by the following circuitEx-NORNORANDNAND30. Which function is realized by the following circuit.\[ (\bar{A} + \bar{B})C + \overline{DE}\](A + B)C + D + EAB + C + DEAB + C(D + E)31. What will be the values of I and J if the following function is to be evaluated. \[ Y = f(A,B) = \bar{A} + B\]I = 1, J = BI = A, J = BI = B, J = 1I = 0, J = B32. Which logic is implemented by the following circuit?NORNANDEX-OROR33. Which is true for the following circuitX = AB + CX = BC + AX = AB + ACX = AC + B34. Black box uses only AND, OR and NOT gates. The function f(A,B,C) = 1 whenever A, B are different and 0 otherwise. In addition the three inputs can never have same values. Which expression is correct for this black box.\[ \bar{A}B + A\bar{B}\]\[ A + \bar{B}C\]\[ \bar{A}\bar{B}\bar{C} + A\bar{B}C\]\[AB + \bar{B}C + \bar{C}\]35. Expression for the output Y is01\[\bar{A}B + A\bar{B}\]\[\overline{AB}\hspace{1pt}.\hspace{1pt}\overline{AB}\]36. Expression for output Y isAB + CD + EF\[\overline{AB} + \overline{CD} + \overline{EF}\](A+B).(C+D).(E+F)\[\overline{(A+B)} + \overline{(C+D)} + \overline{(E+F)} \]37. Boolean expression of the following circuit is\[Y = \overline{AB} + AB + \bar{C}\]\[Y = \bar{A} + A\bar{B} + \bar{C}\]\[Y = A\oplus B + \bar{C}\]\[Y = AB + \bar{C}\]38. Expression for the given figure is\[X = A\overline{BC} + \bar{A}B\bar{C} + \overline{AB}C + ABC \]\[X = \bar{A}BC + A\bar{B}C + AB\bar{C} + \overline{ABC} \]\[ X = AB + BC + AC \]\[\overline{AB} + \overline{BC} + \overline{AC}\]39. The boolean expression implemented by the following figure is\[ F(A,B,C) = \sum (1,2,4,6)\]\[ F(A,B,C) = \sum (1,2,6)\]\[ F(A,B,C) = \sum (2,4,5,6)\]\[ F(A,B,C) = \sum (1,5,6)\]40. With which decoder it is possible to obtain many code conversions ?2 line to 4 line3 line to 8 linenot possible with any decoder4 line to 16 line41. Consider a multiplexer with X and Y as data inputs and Z as control input. What are the connections required to realize the 2-variable boolean function F = T + R with out using any additional hardware?X = R, Y = 1, Z = TX = T, Y = R, Z = TX = T, Y = R, Z = 0X = R, Y = 0, Z = T42. Which one of the following statements is not correct?An 8-input MUX can be used to implement any 4-variable functionA 3 line to 8 line DEMUX can be used to implement any 4-variable functionA 64-input MUX can be built using nine 8-input MUXs.A 6 line to 64 line DEMUX can be built using eight 8-input DEMUXs.Please fill in the comment box below. Time is Up! Time's up (Visited 159 times, 1 visits today)00