Combinational Circuits 1 Welcome to your QUIZ on Combinational Circuits 1 Your Name Please Enter Your Email 1. What is a majority voter circuit? Output is one when above 50 % inputs are false Output is one when above 50 % inputs are true Output is one when 50 % inputs are true None of the above None 2. Karnaugh map is used to minimize the number of flip-flops in a digital circuit minimize the number of gates in a digital circuit minimize the number of gates and fan-in of a digital circuit design gates None 3. Which one of the following can be used as parallel to serial converter? Decoder Digital counter multiplexer Demultiplexer None 4. Which one of the following statements correctly defines the full–adder? a circuit having two inputs used to add two binary digits. It produces their sum and carry as output. a circuit having three inputs used to add two binary digits plus a carry. It produces their sum and carry as outputs. a circuit used in the least significant position when adding two binary digits with no carry into consider. It produces there sum and carry as outputs. a circuit having two inputs and two outputs None 5. Which statements are not true regarding a multiplexer? Selects one of the several inputs and transmits it to a single output. Routes the data from a single input to one of many output Converts the parallel data to serial data Is a combinational circuit None 6. If the output of logic gate is ‘1’ when all its inputs are at logic ‘0’, the gate is either a NAND or EX-OR gate a NOR or an EX-NOR gate an OR or an EX-NOR gate a AND or an EX-OR gate None 7. The number of a 4-line-to-16-line decoders required to make an 8-line-to-256-line decoder is 16 17 32 64 None 8. Four memory chip of 16x4 size have their address busses connected together. This system will be of size. 64x4 16x16 32x8 256x1 None 9. With 4 Booleans variables, how many Booleans expressions can be formed? 16 256 1024 (1 K) 64 K (64x1024) None 10. Which one of the following statements is correct? PROM contains a programmable ‘AND’ array and a fixed ‘OR’ array PLA contains a fixed ‘AND’ array and a programmable ‘OR’ array PROM contains a programmable ‘OR’ array and fixed ‘AND’ array PLA contains a programmable ‘AND’ array and programmable ‘NOR’ array None 11. Which one of the statements describes the operations of multiplexer? A logic circuit used to generate a coded output A logic circuit used to generate F’s complement A logic circuit that accepts two or more inputs and allows one of them at a time to get through the output. A logic circuits that transmits one input to several output lines. None 12. A ROM is used to implement a ‘squarer”, which outputs the square of a 4-bit number. What must be size of ROM? 16 address lines and 16 data lines 4 address lines and eight data lines 8 address lines and eight data lines 4 address lines and 16 data lines None 13. What is the minimum number of NAND gates required to implement \[A + A\bar{B} + A\bar{B}C ?\] 0 1 4 7 None 14. The output of a two level AND-OR gate network is F. What is the output when all the gates were replaced by NOR gates? F Complement of F Dual of F Dual of Complement of F None 15. The output of a two level AND-OR gate network is F. What is the output when all the gates were replaced by NAND gates? F Complement of F Dual of F Dual of Complement of F None 16. Assume that only x and y logic inputs are available, and their complements are not available. What is the minimum number of 2-inputs NAND gates required to implement \[A\oplus B\hspace{2pt} ?\] 2 3 4 5 None 17. A ROM is used to store the table for multiplication of two 8-bit unsigned integer. The size of the ROM required is 256 X 1 64 k X 8 4 k X 16 64 k X 16 None 18. In NOR-NOR configuration, the minimum number of NOR gates needed to implement the function \[X + X\bar{Y} + X\bar{Y}Z \hspace{2pt}\text{is}\] 5 3 2 0 None 19. Output y of the given circuit is 1 0 x Complement of x None 20. The logic circuit realized by the circuit shown below is B Ex-NOR C B Ex-OR C A Ex-NOR C A Ex-OR C None 21. Minimized logic expression of the circuit shown below is \[ \overline{A.\bar{B}.C}\] \[ \overline{\bar{A}.B.\bar{C}}\] \[ \overline{A.B.C}\] \[ \bar{A}.B.\bar{C}\] None 22. The circuit shown below realizes the function \[ (\overline{A + B} + C)(\bar{D}\bar{E})\] \[ (\overline{A + B} + C)(D\bar{E})\] \[ (A + \overline{B + C})(\bar{D}E)\] \[ (A + B + \bar{C})(\bar{D}\bar{E})\] None 23. The logic operations of two combinational circuits shown below are Entirely different Identical Complementary Dual None 24. The half adder circuit in the given figure has inputs AB = 11. The outputs will be X = 0 and Y = 0 X = 0 and Y = 1 X = 1 and Y = 0 X = 1 and Y = 1 None 25. The circuit shown below is an adder circuit a subtractor circuit a comparator circuit a parity generator circuit None 26. The following circuit is functionally equivalent to NOR gate OR gate EX-OR gate NAND gate None 27. What is the required input condition (A, B, C) to make the output X=1 for the below shown circuit (1,0,1) (0,0,1) (1,1,1) (0,1,1) None 28. What is the expression of the Y for the following circuit \[ \overline{(C + D)\oplus (A\oplus B)}\] \[ A \oplus B\] \[ \overline{A \oplus B}\] \[ \overline{C \oplus B \oplus A}\] None 29. Which logic function is implemented by the following circuit Ex-NOR NOR AND NAND None 30. Which function is realized by the following circuit. \[ (\bar{A} + \bar{B})C + \overline{DE}\] (A + B)C + D + E AB + C + DE AB + C(D + E) None 31. What will be the values of I and J if the following function is to be evaluated. \[ Y = f(A,B) = \bar{A} + B\] I = 1, J = B I = A, J = B I = B, J = 1 I = 0, J = B None 32. Which logic is implemented by the following circuit? NOR NAND EX-OR OR None 33. Which is true for the following circuit X = AB + C X = BC + A X = AB + AC X = AC + B None 34. Black box uses only AND, OR and NOT gates. The function f(A,B,C) = 1 whenever A, B are different and 0 otherwise. In addition the three inputs can never have same values. Which expression is correct for this black box. \[ \bar{A}B + A\bar{B}\] \[ A + \bar{B}C\] \[ \bar{A}\bar{B}\bar{C} + A\bar{B}C\] \[AB + \bar{B}C + \bar{C}\] None 35. Expression for the output Y is 0 1 \[\bar{A}B + A\bar{B}\] \[\overline{AB}\hspace{1pt}.\hspace{1pt}\overline{AB}\] None 36. Expression for output Y is AB + CD + EF \[\overline{AB} + \overline{CD} + \overline{EF}\] (A+B).(C+D).(E+F) \[\overline{(A+B)} + \overline{(C+D)} + \overline{(E+F)} \] None 37. Boolean expression of the following circuit is \[Y = \overline{AB} + AB + \bar{C}\] \[Y = \bar{A} + A\bar{B} + \bar{C}\] \[Y = A\oplus B + \bar{C}\] \[Y = AB + \bar{C}\] None 38. Expression for the given figure is \[X = A\overline{BC} + \bar{A}B\bar{C} + \overline{AB}C + ABC \] \[X = \bar{A}BC + A\bar{B}C + AB\bar{C} + \overline{ABC} \] \[ X = AB + BC + AC \] \[\overline{AB} + \overline{BC} + \overline{AC}\] None 39. The boolean expression implemented by the following figure is \[ F(A,B,C) = \sum (1,2,4,6)\] \[ F(A,B,C) = \sum (1,2,6)\] \[ F(A,B,C) = \sum (2,4,5,6)\] \[ F(A,B,C) = \sum (1,5,6)\] None 40. With which decoder it is possible to obtain many code conversions ? 2 line to 4 line 3 line to 8 line not possible with any decoder 4 line to 16 line None 41. Consider a multiplexer with X and Y as data inputs and Z as control input. What are the connections required to realize the 2-variable boolean function F = T + R with out using any additional hardware? X = R, Y = 1, Z = T X = T, Y = R, Z = T X = T, Y = R, Z = 0 X = R, Y = 0, Z = T None 42. Which one of the following statements is not correct? An 8-input MUX can be used to implement any 4-variable function A 3 line to 8 line DEMUX can be used to implement any 4-variable function A 64-input MUX can be built using nine 8-input MUXs. A 6 line to 64 line DEMUX can be built using eight 8-input DEMUXs. None Please fill in the comment box below. Time's up 00
