ASIC Implementation

Power Analysis using Synopsys

In the previous tutorials, simulation and synthesis of digital circuits are described. This tutorial is on Power Analysis using Synopsys. Here, dynamic power consumption of a sequential circuit is estimated. 1.   Open the terminal 2.   Source the synopsys.cshrc 3.   In this experiment, we perform power analysis (dynamic power) of the design using power compiler. 4. 

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ATPG for Combinational Circuits

Automatic Test Pattern Generation and Automatic Test Pattern Generator (ATPGA) is an electronic design automation method/technology used to find an input (or test) sequence that, when applied to a digital circuit, enables automatic test equipment to distinguish between the correct circuit behavior and the faulty circuit behavior caused by defects. This tutorial focuses on ATPG for combinational circuits using Synopsys Tetramax tool. 1.   Open the terminal 2.   Source

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ASIC Tutorials I

Here, we will discuss the tutorials on how to synthesize a Verilog code starting from simulation, syntax checking, code coverage using CADENCE EDA tool. Basic Simulation on CADENCE Linting Code Coverage Logic Equivalence Check Genus Synthesis without Constraints Genus Synthesis with Constraints Genus Synthesis using Scripts Static Timing Analysis using Cadence Tempus +20

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Code Coverage

Code coverage is a basic coverage type which is collected automatically. It tells you how well your HDL code has been exercised by your test bench. In other words, how thoroughly the design has been executed by the simulator using the tests used in the regression. Functional coverage measures how well the functionality of the

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Linting is a process of running a program that will analysis the code for potential errors. This tutorial is for checking errors and warnings in a Verilog code using Cadence tool. Open the terminal Source the cadence.cshrc In a new ASIC lab directory, write a Verilog coded design (in this example fifo.v) Write the linting

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