This is simple IP for the generation of PWM signals through FPGA board. This IP is capable of generating PWM signals of any duty cycle and also PWM signals can have any frequency. This IP has three inputs which are clk, reset, and duty. Users have to provide the required duty cycle of the PWM signal through duty input. This IP has only one output signal which is PWM signal. This IP has only one parameter which is N. It denotes the size of the counter and comparator. This parameter decides the frequency of the PWM signals. More details of this IP can be found in the following link.
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