In our previous tutorial sequential circuits, many different clock divider circuits are introduced. Here in this tutorial, a basic architecture of a programmable clock divider is presented. Clock divider circuits have many use in frequency synthesizers. A basic circuit is presented below in Figure 1.
The circuit is capable of dividing the input clock by N where N can take values from 1 to 15. The circuit passes the same input to the output when N = 1. The circuit is based on a 4-bit loadable counter and a 4-bit comparator. The value of N is decremented and passed to the input of the loadable counter. This increment is done by a simple 4-bit subtractor. The output of the loadable counter is connected to the input and thus the counter act as mod counter. The RSH1 block is a simple 1-bit right shift block. This block has another output which is the residual bit after shifting. The bit selects the negative or positive edge triggering for the dff block.
The above mentioned programmable clock divider can be scaled to increase the range of clock division. This can be done by increasing the width of the loadable counter and comparator.
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