Sequential Multiplier is an old method to multiply two binary numbers. But it is also relevant in many architectures and it is the base of many newly developed multiplication techniques. The multiplication between a and b is shown below.
The multiplication between two operands a and b can be considered as add the operand a total b times. For example, s = 5 X 3 = 5 + 5 + 5 = 15. Serially 5 is added total 3 times to compute the final result. Thus total one adder is sufficient. For a word length of 4-bits, width of the multiplication result is 8-bit. So, an 8-bit adder is required.
An alternative method is shift and add method. If any bit in the multiplier (b) is 0 then the multiplicand (a) is added with zero. An adder is used which is of the same length as of the operands. Output of the adder and the multiplier is augmented in a register bank. After each addition contents of the register bank is shifted right. A scheme of serial addition is shown below.
The start signal starts the multiplication process. It loads the multiplicand (a) in a register and also loads the multiplier (b) in another register. Each D flip flop is controlled by a control signal. The DFFs shifts data to the right only when the control signal is high. The counter tracks the latency of the multiplier. The PG block is there to generate the enable signal for the counter and the bottom register. The start pulse generates the en signal.
The simulation of the serial multiplier is shown below.
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