`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    16:04:57 03/11/2020 
// Design Name: 
// Module Name:    Prog_clk_div 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module prog_clk_divider(clk,reset,en,N,clk_out);
input [3:0] N;
output clk_out;
wire [3:0] q1,q2,N1;
input clk,reset,en;
parameter data = 4'b0000;

assign N1 = N -4'b0001; //4-bit subtractor
loadcnt_up cnt(q1,data,tc,en,reset,clk,tc,N1);///4-bit loadable counter

rsh1 shift(N,q2,rs);////wired Right Shift Block
comparator4 cmp(q1,q2,1'b0,1'b0,1'b1,,gt,); /// 4-bit comparator

mux_df mx(clk,~clk,rs,clk1);

dff df(t1,reset,clk1,gt);
assign s1 = ~N[3] & ~N[2] & N[1] & ~N[0];///check for N = 2;
assign s2 = ~N[3] & ~N[2] & ~N[1] & N[0];///check for N = 1;
assign clk_out = ~s2 & (t1 | gt) | (s1 & q1[0]) | (s2 & clk);
endmodule

module loadcnt_up(q,b,load,en,reset,clk,tc,lmt);
input clk,load,en,reset;
input [3:0] b,lmt;
output [3:0] q;
output tc;
wire a1,a2,a3,t1,t2,t3,t4,en1;
wire [3:0] d;
assign d[0] = ~q[0];
assign d[1] = q[1]^q[0];
assign d[2] = q[2]^(q[1]&q[0]);
assign d[3] = q[3]^(q[2]&q[1]&q[0]);
mux_df m1(d[0],b[0],load,t1);
dff1 d1(q[0],clk,reset,t1,en1);
mux_df m2(d[1],b[1],load,t2);
dff1 d2(q[1],clk,reset,t2,en1);
mux_df m3(d[2],b[2],load,t3);
dff1 d3(q[2],clk,reset,t3,en1);
mux_df m4(d[3],b[3],load,t4);
dff1 d4(q[3],clk,reset,t4,en1);
assign en1 = load | en;
assign a1 = q[0] ~^ lmt[0];
assign a2 = q[1] ~^ lmt[1];
assign a3 = q[2] ~^ lmt[2];
assign a4 = q[3] ~^ lmt[3];
assign tc = a1 & a2 & a3 & a4;
endmodule

module dff(q,reset,clk,d);
output reg q;
input reset,d,clk;
initial begin q=1'b0; end
always @ (posedge clk)
if (reset)
q <= 1'b0;
else 
q<=d;
endmodule

module dff1(q,clk,reset,d,en);
output reg q;
input reset,d,clk,en;
initial begin q=1'b0; end
always @ (posedge clk)
if (reset)
q <= 1'b0;
else if(en) 
q<=d;
else
q<=q;
endmodule

module mux_df(a,b,s,y);
input s,a,b;
output y;

assign y = (s)? b:a;
endmodule

module comp_1bit(a,b,lt,eq,gt);///////////////1-bit comparator

    input a,b;
    output lt,gt,eq;
	 wire abar,bbar;

assign abar = ~a;
assign bbar = ~b;
assign lt = abar & b;
assign gt = bbar & a;
assign eq = ~(lt|gt);
endmodule

module comparator4(A,B,LT1,GT1,EQ1,LT2,GT2,EQ2);///////////////4-bit comparator
    input [3:0] A,B;
    output LT2,GT2,EQ2;
	 input LT1,GT1,EQ1;
    

wire x30,x31,x32,x20,x21,x22,x10,x11,x12,x00,x01,x02;
wire x40,x41,x42,x50,x51,x52,x61,x62;
comp_1bit  c3(A[3],B[3],x30,x31,x32);
comp_1bit  c2(A[2],B[2],x20,x21,x22);
comp_1bit  c1(A[1],B[1],x10,x11,x12);
comp_1bit  c0(A[0],B[0],x00,x01,x02);

assign x40 = x31 & x20;
assign x41 = x31 & x21 & x10;
assign x42 = x31 & x21 & x11 & x00;

assign x50 = x31 & x22;
assign x51 = x31 & x21 & x12;
assign x52 = x31 & x21 & x11 & x02;
assign EQ = (x31 & x21 & x11 & x01);

assign EQ2 = EQ & EQ1;
assign x61 = EQ & LT1;
assign x62 = EQ & GT1;

assign LT2 = (x30 | x40 | x41 | x42) | x61;
assign GT2 = (x32 | x50 | x51 | x52) | x62;

endmodule

module rsh1(a,b,rs);
    input [3:0] a;
    output [3:0] b;
	 output rs;
    
assign {b[3],b[2:0]}= {1'b0,a[3:1]};
assign rs = a[0];

endmodule