Linting is a process of running a program that will analysis the code for potential errors. This tutorial is for checking errors and warnings in a Verilog code using Cadence tool.
- Open the terminal
- Source the cadence.cshrc
- In a new ASIC lab directory, write a Verilog coded design (in this example fifo.v)
- Write the linting test syntax as shown below with your design code. Lab]$ irun –superLint fifo.v
- Check the folder contents after exiting from FormalVerifier. It will have few log files, which we have to check for improving our coding style.
- Check the file rtlchecks.log and modelchecks.log. We have to figure out the issues in the design code.
- Verify the reason behind the warnings and errors if any, and analyze the code accordingly.
Faculty Advisor: Prof. Kamalakanta Mahapatra
Instructor: K Sudeendra, Teaching Assistants: S K Ram, J P Mohanty
The VLSI laboratory at ECE Department of NIT Rourkela is obliged towards the support and encouragement of Ministry of Electronics and Information Technology, Government of India. The overall activities is purely supported by the Special Manpower Development Program for Chips to System Design (SMDP-C2SD) project.