GENUS Synthesis Without Constraints

In this tutorial Cadence GENUS Synthesis without Constraints is presented.

1. Open the terminal and type csh

2. Source the cadence.cshrc. After sourcing the file, check whether genus is installed in the current system or not by typing the below command

[sudi@sankh]which genus</span> <!-- /wp:paragraph -->  <!-- wp:paragraph --> 3.  In ASIC lab folder, make a new directory. Make design.v and testbench.v ready. Clear the syntax errors. Simulate and confirm the functionality through simvision simulations (Follow post for <a href="">simulation</a>). <!-- /wp:paragraph -->  <!-- wp:image {"id":2164,"sizeSlug":"large"} --> <figure class="wp-block-image size-large"><img src="" alt="" class="wp-image-2164"/></figure> <!-- /wp:image -->  <!-- wp:paragraph --> 4. We are doing synthesis in this lab. We use Cadence synthesis tool : GENUS Synthesis Solution. Type the command as below and check path of genus is echoed or not in your machine: - <!-- /wp:paragraph -->  <!-- wp:image {"id":2165,"sizeSlug":"large"} --> <figure class="wp-block-image size-large"><img src="" alt="" class="wp-image-2165"/></figure> <!-- /wp:image -->  <!-- wp:paragraph --> 5. We need standard cell libraries for synthesis. So check the path to the standard cell libraries in your workstations. You <strong>do not need </strong>to copy the files to your working folder. <!-- /wp:paragraph -->  <!-- wp:paragraph --> 6. Execute genus -gui for invoking the EDA Synthesis tool <!-- /wp:paragraph -->  <!-- wp:paragraph --> <span class="has-inline-color has-vivid-cyan-blue-color">[sudi@sankh] genus –gui

7. Minimize the gui and follow below instructions, mentioning the proper path for linking the saed90nm library files

genus@root:> read_libs saed90nm_typ.lib genus@root:> read_hdl -v2001 counter.v

genus@root:> elaborate

genus@root:> synthesize -to_mapped

8. Save the gate level netlist

genus@root:> write_hdl > design_netlist.v

9. Find the design_netlist.v file created in the working directory. A cmd and a log file will also be generated that stores the current activities along with a fv verification file.

10. Record the area, timing and power by following the below commands

genus@root:> report_units

genus@root:> report_gates

genus@root:> report_utilization

genus@root:> report_sequential

genus@root:> report_power

11. Simulate the design as you did in earlier experiment. Check the simulation using this netlist file. (Blindly don’t follow the manual. Give the correct path based on where you have the libs folder copied. Use the command “pwd” to get path)

[sudi@sankh]$ ncverilog counter_tst.v design_netlist.v +access+rw -v saed90nm.v +gui

For more details check the Genus_gui document in the installed folder

Post Credit

Faculty Advisor: Prof. Kamalakanta Mahapatra

Instructor: K Sudeendra, Teaching Assistants: S K Ram, J P Mohanty

VLSI Laboratory

The VLSI laboratory at ECE Department of NIT Rourkela is obliged towards the support and encouragement of Ministry of Electronics and Information Technology, Government of India. The overall activities is purely supported by the Special Manpower Development Program for Chips to System Design (SMDP-C2SD) project.

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