In the previous tutorials, simulation and synthesis of digital circuits are described. This tutorial is on Power Analysis using Synopsys. Here, dynamic power consumption of a sequential circuit is estimated.
1. Open the terminal
2. Source the synopsys.cshrc
3. In this experiment, we perform power analysis (dynamic power) of the design using power compiler.
4. In a ASIC lab directory, create design.v. Create the testbench.v for design.v and simulate the design in VCS.
5. After simulation of design, it creates inter.vpd. Convert the vpd to vcd and vcd to saif format.
[sudi@sankh powerana]$ vpd2vcd inter.vpd inter.vcd
6. (VCD: Value Change Dump and SAIF : Swithcing Activity Interchange format)
7. Once the simulation snapshot is stored in VCD or VPD format, we can open it using any waveform viewer. (dve or simvision). Commands are below: –
8. Power compiler is a integral part of Design Vision and accepts only SAIF files. So convert VCD to SAIF as below: –
9. Open design_vision. Read the library and design into design vision. Compile the design and report power.
10. To save the power report into a separate text file use the following command: –
11. Open the new terminal. Go to the power analysis folder and open the Power1 file in gedit.
12. Now read the saif file into design_vision as below, and do compile design again (re- synthesize). And execute report_power.
13. report_power again. Compare the dynamic power in Power1 and Power2 reports.
14. Change the stimulus (input patterns) in the testbench.v and analyze the dynamic power for different stimulus.
15. Do the power analysis for all designs.
Instructor: K Sudeendra, Teaching Assistants: S K Ram, J P Mohanty
The VLSI laboratory at ECE Department of NIT Rourkela is obliged towards the support and encouragement of Ministry of Electronics and Information Technology, Government of India. The overall activities is purely supported by the Special Manpower Development Program for Chips to System Design (SMDP-C2SD) project.