Our objective is to divide A by B where both A and B can be positive or negative. The division operation can be expressed as by the following equation by considering 4 bit data width.
where Q is the quotient and R is the remainder. The division operation is carried out by subsequent stages where each stage determines a quotient bit. Thus it is called an array divider.
In the first stage to find the bit Q3, B is left shifted by 3 bits and subtracted from A. The quotient bit Q3 is 1 if the difference is zero or positive. If the difference is negative, Q3 is 0 and the value of A is passed to the next stage. This technique is simply the restoring division discussed in the previous post. The division operation is explained by an example where A = 1100 and B = 0010. The unsigned divider for 4-bit data width is shown below.
From the above example it is clear that to compute Q3, B0 is subtracted from A3 only when other bits of B are zero. This logic is implemented in the first stage. Similarly to compute Q2, bits B1 and B0 are needed to be subtracted thus two sub blocks are used. The block diagram of the sub block is also given in the above figure. It consists of a full subtractor and a Mux.
The above example is shown for division by unsigned numbers. The signed division can be done easily by adopting this division method. The input signed operands (Two’s compliment representation) are needed to converted to unsigned operands and at the output the quotient and residual are also needed to be converted to signed operands depending on the sign of input operands.
The above divider produces a quotient (Q) and remainder (R) but the practical use of divider involve generation of fractional bits. A Verilog code of a complete pipelined 18-bit signed divider is given in this bit. 8-bits are used for integer part and 10-bits are used for fractional part. To generate fractional result, 10 more stages are added to the previous stages. This divider can be modified accordingly to requirement of quotient and fractional bits.