Seven Segment Display Controller

Almost every FPGA boards are having seven segment display elements. These displays are very useful for displaying data in he form of BCD. Suppose, one design is implemented on FPGA and display of the result is required. Then the result of the design can be displayed on these seven segment displays. Seven segment displays are having seven segments and using these seven segments any digits from 0 to 9 can displayed. A seven segment display controller is necessary to display BCD digits. In this the seven segment display controller is explained.

A seven segment display controller has three main parts which are clock division, controller part and binary to BCD conversion part. Each part is shown below.

Clock Division

Clock division is necessary for seven segment controller. This is because all the elements of seven segment displays are generally serially connected in an FPGA board to save pins. A 7-bit data can be displayed on any of the elements. Generally 3-4 for seven segment elements are connected in an FPGA board. According to the clock, data is displayed on the elements. Clock can not be too fast as sampling of data must be proper. Also clock can not be too slow otherwise user has to wait to give next data input.

always @ (posedge clk or  posedge reset)
begin
if (reset)
COUNT <= 0;
else 
COUNT <= COUNT + 1;
end

assign CLK_7_SIG = COUNT[15];

Seven Segment Display Controller Part

In this part, all the segments and selection lines are assigned. Each element of seven segment displays has a select line. If this line is active then only data can be displayed on that element. One select line is there to enable the decimal point which is placed after each seven segment display. Finally, seven segment display has 7 segments. Based on the inputs on these segments, a digit is displayed. Generally all the select lines are active low. Means, if there is high in the select line, then particular select line is disabled.

always @(posedge CLK_7_SIG or posedge reset)
begin
if (reset == 1 || BCD == 4'b0100)
BCD <= 0;
else 
BCD <= BCD + 1;
end

always @(posedge CLK_7_SIG )
begin
	case (BCD)
		3'b000 : begin
			sel_disp1 <= 1;
			sel_disp2 <= 0;
			sel_disp3 <= 0;
			sel_disp4 <= 0;
			COUNT_BCD <=data_disp_1; end
		3'b001 : begin
			sel_disp1 <= 0;
			sel_disp2 <= 1;
			sel_disp3 <= 0;
			sel_disp4 <= 0;
			COUNT_BCD <=data_disp_2; end
	
		3'b010 : begin
			sel_disp1 <= 0;
			sel_disp2 <= 0;
			sel_disp3 <= 1;
			sel_disp4 <= 0;
			COUNT_BCD <=data_disp_3; end
		3'b011 : begin
			sel_disp1 <= 0;
			sel_disp2 <= 0;
			sel_disp3 <= 0;
			sel_disp4 <= 1;
			COUNT_BCD <=data_disp_4; end
default : begin
			sel_disp1 <= 0;
			sel_disp2 <= 0;
			sel_disp3 <= 0;
			sel_disp4 <= 0;
			COUNT_BCD <=data_disp_1; end
	endcase end
	
	always @* begin
	case(COUNT_BCD)
	   4'b0000 : seg =  8'b11000000;   //0
		4'b0001: seg =  8'b11111001;   //1
		4'b0010 : seg =  8'b10100100;  //2
		4'b0011 : seg =  8'b10110000;    //3
		4'b0100 : seg =  8'b10011001;   //4
		4'b0101 : seg =  8'b10010010;  //5
		4'b0110 : seg =  8'b10000010;    //6
		4'b0111 : seg =  8'b11111000;   //7
		4'b1000 : seg =  8'b10000000;   //8
		4'b1001 : seg =  8'b10010000;    //9
		4'b1010 : seg =  8'b10001000;    //A
		4'b1011 : seg =  8'b10000011;    //b
		4'b1100 : seg =  8'b11000110;    //C
		4'b1101 : seg =  8'b10100001;   //d
		4'b1110 : seg =  8'b10000110;    //E
		4'b1111 : seg =  8'b10001110;    //F
   endcase end

Binary to BCD Conversion

The last part is the conversion of binary data to BCD data. There are many to convert binary data to BCD. One simple behavioral method is shown below

module binbcd16(bin,bcd);
	input [15:0] bin;
	output [18:0] bcd;

	reg [18:0] bcd;
	reg [35:0] x;
	integer i;
  always @(bin)
  begin
    for(i = 0; i <= 35; i = i+1)
	x[i] = 0;
    x[18:3] = bin;
    for(i = 0; i <= 12; i = i+1)
    begin
	if(x[19:16] > 4)	
		x[19:16] = x[19:16] + 3;
	if(x[23:20] > 4) 	
		x[23:20] = x[23:20] + 3;
	if(x[27:24] > 4) 	
		x[27:24] = x[27:24] + 3;
	if(x[31:28] > 4) 	
		x[31:28] = x[31:28] + 3;
	if(x[35:32] > 4) 	
		x[35:32] = x[35:32] + 3;
	x[35:1] = x[34:0];
    end      
    bcd = x[35:16];	
  end 
endmodule
Verilog code of Seven Segment Display Controller (20 downloads)
(Visited 112 times, 1 visits today)
Shopping Cart