A video controller generates the synchronization signals and outputs data pixels serially through the VGA port of the FPGA board. The synchronization signals generator circuit (vga_sync) generates the timing and control signals. The hsync and vsync signals control the horizontal and vertical scans. The pixel_x and pixel_y signals specify the current location of the pixel. […]
Interfacing VGA display with FPGA Read More »
In the previous tutorials, we have discussed techniques which can be used to achieve fast multiplication. But when the multiplicand and the multiplier are same, there must be some way to simplify the implementation. Thus squaring operation does not require the full length hardware of a multiplier. In applications where a squaring operation is required,
Dedicated Square Block Read More »
Chris Wallace in 1964 gave some suggestions on fast multiplication. In order to achieve high speed without consuming extra hardware he suggested techniques. He proposes to use the basic HAs and FAs as basic elements for operand reduction. He applied operand reduction in parallel layers and achieve better speed. The steps are Obtain the partial products
Wallace and Dedda Multiplier Design Read More »
Booth’s algorithm is a powerful technique to achieve fast multiplication. Booth’s algorithm can be employed either sequentially or with the help of fast addition methods or in the form of array multiplication. In this tutorial, Booth’s Radix-4 algorithm is used to form an architecture to multiply two 6-bit numbers in the form of array multiplier.
Booth’s Array Multiplier Read More »
Several techniques are suggested for partial products accumulation. Some of them targets to reduce the logic elements to reduce hardware complexity whereas some of them targets to reduce numbers of levels in the tree of partial products to achieve high speed. As the number of levels increases irregularity in the design also increases. The irregularities
Alternative Techniques for Partial Product Accumulation Read More »
Earlier we have discussed how the partial products for a unsigned multiplier can be accumulated using suitable organization and consuming minimum number of counters. In this section, accumulation will be done by considering negative partial products. If some of the partial products are negative numbers represented in two’s complement number system, then matrix of bits
Accumulation of Partial Products for Signed Numbers Read More »
A basic circuit to accumulate two single bits is a half-adder (HA) and a full-adder (FA) accumulates three bits. Thus a HA is called as 2:2 counter and a FA is called a 3:2 counter. Again an HA is hardware efficient than a FA. Carry save adders (CSA) operates on multiple operands. A basic CSA
Accumulation of Partial Products for Unsigned Numbers Read More »
Like Booth’s multiplication algorithm another method reduction of partial products is implementing higher multipliers by smaller ones. The larger multiplier blocks can be realized using smaller multiplier blocks. A multiplier can be realized using four multiplier blocks. This is based on the following equation where is the most significant halve of A, is the most
Implementing Large Multiplier Using Smaller ones Read More »
Booth’s multiplication algorithm is based on the fact that fewer partial products are needed to be generated for consecutive ones and zeros. For consecutive zeros, a multiplier only needs to shift the accumulated result to the right without generating any partial products. For example, the accumulated result is shifted one bit right for every ‘0’
Booth’s Multiplication Algorithm Read More »
Bhakshali Algorithm This method for finding an approximation to a square root or square root reciprocal was described in an ancient Indian mathematical manuscript. This algorithm is quartically convergent. The iterative equations are The variable approaches zero and holds the value of square root. Two variable iterative method This method is used to find square
Fast Computation of Square Root and its Reciprocal Read More »
The Non-Restoring (NR) algorithm for square root operation is similar to the NR algorithm for division operation. It is similar to the Restoring algorithm but it has no restoring step. But in implementation of this two algorithms, both are very similar. The NR algorithm for square root operation is shown below in Fig. 1. In
Non-Restoring Algorithm for Square Root Read More »
The Restoring algorithm for square root is similar to the Restoring division algorithm. Let X is the positive radicand and its square root is represented as , when n is the total number of iterations. The bits of Q are generated in n number of steps, one bit per iteration. The is expressed as The
Restoring Algorithm for Square Root Read More »
An FPGA is a device that contains a matrix of reconfigurable gate array logic circuitry. When a FPGA is configured, the internal circuitry is connected in a way that creates a hardware implementation of the software application. Unlike processors, FPGAs use dedicated hardware for processing logic and do not have an operating system. FPGAs are
FPGA: Basic Overview Read More »
In this part, a tutorial on the FPGA implementation of digital systems is discussed. A simplified version of FPGA based design flow is given in the following diagram. Lets consider an example to illustrate the FPGA implementation procedure. The circuit shown in Fig. 2 is considered as a test circuit. Design Entry There are different
FPGA IMPLEMENTATION – Step By Step Read More »
Power consumption is an important key design metric to determine performance of a chip. In VLSI circuit point of view, total power consumption can be due to various factors. In general total power consumption is summation of static power consumption ( ) and dynamic power consumption ( ) . But in this section as we
Dynamic Power Consumption Estimation Read More »
