Interfacing ADC with FPGA

Interfacing ADC with FPGA board is important when we need to acquire an analog signal to process it in FPGA. In many academic projects we are asked to demonstrate the real time application of a digital system implemented on FPGA. In doing that, we find it difficult to interface an ADC chip with FPGA as a separate HDL code is required to write. In this blog, a tutorial on interfacing ADC with FPGA is given. Here, we have chosen an ADC chip to interface with FPGA board which can be applicable to other chips also.

The selected ADC chip (MCP3008) is a product of Microchip Company. It is a 10-bit ADC chip having 8 input channels. It is capable of sampling at 200 ksps at VDD of 5.5 V. Minimum clock frequency is 18\times f_{sample} . More details about the ADC chip can be found in the specification document of the chip.

The pin diagram of the chip is shown in Figure 1.

Figure 1: MCP3008 Pins Arrangement

The ADC inside the chip is SAR logic based. It has 8 channels and input can be selected through any channel. The basic functional diagram is shown in Figure 2.

Figure 2: Functional Diagram of the SAR based ADC

Nowadays every chip is either SPI or I2C protocol based. The chip we are considering here is SPI based. The shift register outputs data serially through the pin D_{OUT}. It has a CLK pin at which frequency should be kept at 18 times higher than the sampling frequency. The pin \bar{CS}/SHDN is for controlling the SAR logic of the ADC and it is an active low signal. The serial pin D_{IN} provides the control word. The timing diagram is shown in Figure 3.

Figure 3: Timing diagram for SPI interface

The SPI protocol based ADC chip is interfaced with FPGA by writing a Verilog code. The Verilog code written here is FSM based as we are less concerned about the performance of the code. IN that we have defined separate states for every status on the D_{IN} pin. The code receives the output data and make a valid word. The start bit is kept high and the next bit defines how we take analog signals. If it is high then it is single ended and if low then it is differential. The next three bits are for selecting input channels. The SPI based controlling of the ADC chip is shown in Figure 4.

Figure 4: Controlling of a SPI based ADC chip

To demonstrate that the ADC chip is interfaced with FPGA, we haven chosen NEXYS 4 DDR board. The ADC chip is mounted on a PCB along with other chips. We have taken a DC voltage source to feed analog input to the ADC chip. We have varied the voltage source from 0 to 3.3 volt which is maximum voltage of the FPGA board. The experimental setup is shown in Figure 5. Here we can see that all the 10 LEDs are blinking when voltage is 3.3.

Figure 5: Experimental Setup for Interfacing ADC with FPGA

The formula for interpreting the digital value from an 10-bit ADC chip is

Digital Code = \frac{1024\times V_{IN}}{V_{REF}}

Click here to download the Verilog code.

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3 thoughts on “Interfacing ADC with FPGA”

  1. Hey Hi,
    It is such a nice article and was very helpful.
    Can you please send the circuit wiring of FPGA to ADC (pin connections between ADC and FPGA)

    Thank you 🙂

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