Square of a number can also be computed using VEDIC arithmetic formulas. Square computation is generally faster and hardware efficient than the complete multipliers. Similarly a VEDIC square block is hardware efficient than the multiplier block. Square of an operand is computed using the Dwandwa Yoga or Duplex method. Any number can be represented as […]
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Multiplier is a major block in designing digital systems. Several algorithms are reported in literature to implement fast multipliers. VEDIC multiplication algorithm is another option to implement an efficient multiplier. This work discuses the VEDIC multiplier. There are 3 methods to implement multiplication in VEDIC mathematics. Out of three, only one method is generic method
The impulse response of a Finite Impulse Response (FIR) filter is of finite duration as it settles to zero in finite time. In comparison to the Infinite Impulse Response (IIR) filters, there is no feedback in FIR filter. This feature makes the FIR filter always stable. Another important feature of FIR filter is that it
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K-means algorithm is very popular because of its simplicity. This is an iterative algorithm which tries to partition a dataset into K groups. K-means algorithm tries to group the similar data samples in a cluster in every iteration. This is carried out based on some formulas which computes the similarity between two vectors. This algorithm
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In our previous tutorial sequential circuits, many different clock divider circuits are introduced. Here in this tutorial, a basic architecture of a programmable clock divider is presented. Clock divider circuits have many use in frequency synthesizers. A basic circuit is presented below in Figure 1. The circuit is capable of dividing the input clock by
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In the previous tutorials, we have discussed about the fixed point architectures. Majority of FPGA based architectures are fixed point based. In the fixed point architectures, the number of bits reserved for integer and fractional part is fixed. Thus there is a limitation in representing wide range of numbers. This limitation results truncation error at
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The floating point to fixed point conversion is necessary to interface a floating processor to a fixed point implementation. So that there maintains a smooth transition from one type of architecture to another. The steps involved in this conversion are Concatenate the hidden bit and add leading zeros according to the fixed point length. Find
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Floating point comparison is similar to the comparison of two numbers in fixed point arithmetic as discussed in the post for combinational circuits. The same architecture can be used here also. Yet this architecture is discussed here to have clear idea about floating point comparison. The steps involving the comparison of two floating point numbers
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The architecture for floating point square root computation can also be designed in the same way the other architectures are designed. Various fixed point square root architectures are discussed in the blog for square root computation. There are some modifications needed to convert a fixed point square root architecture to compute square root of floating
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Performing division is a difficult task as we have seen in case of fixed point arithmetic also. Divider architectures are complex to implement. Floating point division is nothing but a fixed point division with some extra hardwares to take care for the exponents. This extra hardwares make the divider circuit more complex. A floating point
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Floating point multiplication is comparatively easy than the floating point addition algorithm but off course consumes more hardware than fixed point multiplier circuit. Major hardware block is the multiplier which is same as fixed point multiplier. This multiplier is used to multiply the mantissas of the two numbers. A floating point multiplication between two numbers
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Compared to a fixed point addition and subtraction, a floating point addition and subtraction is more complex and hardware consuming. This is because exponent field is not present in case of fixed point arithmetic. A floating point addition of two numbers and can be expressed as Here, it is considered that . In this case,
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Generally the FPGA based architectures or ASIC based implementations are fixed point arithmetic based. But the majority of dedicated controllers are floating point based. It may require to interface a FPGA to a micro controller and then a fixed point to floating point conversion unit will be required. In order to discuss the floating point
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In a binary number, leading zeros are the zero digits in the most significant positions of data, up to the position in which the first one is present. For a binary number the leading leading zero count is 4. Leading zero counter is a very important combinational circuit in designing the floating-point architectures to do
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Interfacing ADC with FPGA board is important when we need to acquire an analog signal to process it in FPGA. In many academic projects we are asked to demonstrate the real time application of a digital system implemented on FPGA. In doing that, we find it difficult to interface an ADC chip with FPGA as
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