Code coverage is a basic coverage type which is collected automatically. It tells you how well your HDL code has been exercised by your test bench. In other words, how thoroughly the design has been executed by the simulator using the tests used in the regression. Functional coverage measures how well the functionality of the […]
Linting is a process of running a program that will analysis the code for potential errors. This tutorial is for checking errors and warnings in a Verilog code using Cadence tool. Open the terminal Source the cadence.cshrc In a new ASIC lab directory, write a Verilog coded design (in this example fifo.v) Write the linting
This tutorial is on functional simulation of digital circuits on Genus tool of CADENCE software for ASIC Implementation. Open the terminal Source the cadence.cshrc Check whether the commands are working as below: – Create a directory for saving files as below Create design_file.v as shown below: – (gedit counter.v) Check the syntax of design.v (in
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In this tutorial, we will discuss another architecture for Matrix Multiplication. This architecture is a systolic matrix multiplier. A systolic architecture is a homogeneous network of tightly coupled data processing units. Each data processing units compute partial result independently. The systolic architectures are very suitable for implementing any kind of digital systems as they are
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Apart from scalar-vector multiplication, Vector-Vector multiplication is another very important arithmetic operation in implementing signal or image processing algorithms. The matrix multiplications can also be achieved through vector-vector multiplication which is also called as inner product computation. In this tutorial, we will discuss multiplication of matrix A (6X6) with matrix B (6X6) using Vector-Vector multiplication.
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Scalar-Vector multiplication is a very important arithmetic operation in implementing signal or image processing algorithms. In this tutorial, we will discuss the hardware for multiplication between a 6X3 Matrix (A) and a 3X1 Matrix (B) and the result is a 6X1 column vector (C). This multiplication is shown below in Figure 1. This multiplication can
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Here a simple Behavioral coding of the Selection Sort algorithm is given. This code is written in such a way that it can support any number of inputs with any size. This code is a basic version of the Selection sort algorithm and sorts the given array in one clock cycle. The code is written
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Here a simple Behavioral coding of the Insertion Sort algorithm is given. This code is written in such a way that it can support any number of inputs with any size. This code is a basic version of the Insertion sort algorithm and sorts the given array in one clock cycle. The code is written
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Here a simple Behavioral coding of the Bubble Sort algorithm is given. This code is written in such a way that it can support any number of inputs with any size. This code is a basic version of the Bubble sort algorithm and sorts the given array in one clock cycle. The code is written
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The parallel sort architecture described in [1] for n=8 has a regular structure. This structure can be divided in similar stages. This structure consumes 23 basic node blocks but sorts 8 data elements in just 1 iteration. A serial sort architecture can be derived from this structure which sorts 8 data elements in some iterations.
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Bubble sort is a very popular and a basic technique to sort an array elements. This technique is hardly used anywhere due to its high computational complexity. But here the concept of Bubble sort is demonstrated. In this technique, adjacent elements are sorted in every run. This way after some runs the array is sorted.
Marge parallel sort is based on dividing the array of numbers into sub arrays and then marging them one by one. Here a parallel sorting structure is shown for n = 8 based on Marge sort technique. This sort structure is hardware efficient than the other parallel structures discussed previously. First the array of four
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Here an alternate parallel sorter is discussed for n=8. Compared to the parallel sorting structure shown in the post for Bitonic sort, here same type of basic nodes are used. The BN blocks sort two elements in descending order. This sorting algorithm works on the principle of sorting the adjacent elements. This structure consumes 25
Batcher’s Bitonic sorter is a parallel sorting algorithm whose main operation is a technique for merging two Bitonic sequences. A Bitonic sequence is the concatenation of an ascending and a descending sequence of numbers. For example, 2, 4, 6, 8, 9, 24, 6, 3, 2, 0 is a Bitonic sequence. To sort a sequence of
Majority of digital filters implemented in the digital systems are Finite Impulse Response (FIR) filters. Infinite Impulse Response (IIR) filters can produce same frequency response but with less co-efficients and delay elements compared to FIR filters. But use of IIR filters is limited to the low frequency applications. This is due to the fact that
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