In the previous three tutorials, we have learned how prepare the files which are needed to start the placement and routing using INNOVUS. In this tutorial, a basic tutorial on how to perform placement and routing using INNOVUS is given. This is a very fundamental and only covers the basic ideas and follows the tutorial […]
Placement and Routing using INNOVUS Read More »
In the previous tutorial on Placement And Routing For ASIC, we have seen that one I/O file is also important. This tutorial is on I/O file setup for PnR using INNOVUS. An I/O file is for custom arrangement of I/O pins and I/O pads. This file is optional if the final sign-off analysis is not
I/O file setup for PnR using INNOVUS Read More »
In the previous tutorial on Placement and Routing using INNOVUS, we have seen how to open the tool and how to import all the files. In this tutorial, we will discuss how to prepare view definition file by performing Multi Mode Multi Corner (MMMC) analysis. MMMC analysis is very important to perform, so that the
MMMC file setup for PnR using INNOVUS Read More »
In the previous tutorial, we have presented a basic tutorial on Placement and Routing for ASIC. This tutorial is the first step towards Placement and Routing using INNOVUS tool. We will cover very basics of Placement and Routing using INNOVUS as it is a huge area and many tutorials are available on internet. Here, we
Importing Files for PnR using INNOVUS Read More »
The previous tutorials [Tutorial 1, Tutorial 2] are on the simulation and synthesis of Verilog files. In addition to these we have also performed linting, code coverage, logic equivalence check, DFT, ATPG, power analysis and Timing analysis using CADENCE and SYNOPSYS tools. Till now we have not discussed anything about the step Placement and Routing
Placement and Routing for ASIC Read More »
