Marge parallel sort is based on dividing the array of numbers into sub arrays and then marging them one by one. Here a parallel sorting structure is shown for n = 8 based on Marge sort technique. This sort structure is hardware efficient than the other parallel structures discussed previously. First the array of four […]
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Parallel Sorting Architectures Bitonic Sorter An alternative parallel Sorter Merge Parallel Sorter Serial Sorting Architectures Bubble Sorter Insertion Sorter Serial Sort Architecture Bubble Sort Behavioral Insertion Sort Behavioral Selection Sort Behavioral Design of a Sorting Processor to Sort Serial Data Stream 00
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Here an alternate parallel sorter is discussed for n=8. Compared to the parallel sorting structure shown in the post for Bitonic sort, here same type of basic nodes are used. The BN blocks sort two elements in descending order. This sorting algorithm works on the principle of sorting the adjacent elements. This structure consumes 25
Batcher’s Bitonic sorter is a parallel sorting algorithm whose main operation is a technique for merging two Bitonic sequences. A Bitonic sequence is the concatenation of an ascending and a descending sequence of numbers. For example, 2, 4, 6, 8, 9, 24, 6, 3, 2, 0 is a Bitonic sequence. To sort a sequence of
Majority of digital filters implemented in the digital systems are Finite Impulse Response (FIR) filters. Infinite Impulse Response (IIR) filters can produce same frequency response but with less co-efficients and delay elements compared to FIR filters. But use of IIR filters is limited to the low frequency applications. This is due to the fact that
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Ancient Indian VEDIC Mathematics consists of sixteen mathematical formulae reconstructed from the Atharvaveda. It is recognized as an a efficient technique for enhancing the mathematical skills of students. The arithmetic operations like multiplication, division, square root, cubing, squaring and finding cube root are time consuming processes for machineas well as man. VEDIC mathematics results in
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Apart from the multiplication and square, finding cube of a number is an another important operation in signal processing. The cube of a number can be computed using Anurupya Sutra which is the subsutra of Ekadhikena Purvena. VEDIC Cube architecture is efficient in terms of hardware and also in terms of delay. Cube of a
Square of a number can also be computed using VEDIC arithmetic formulas. Square computation is generally faster and hardware efficient than the complete multipliers. Similarly a VEDIC square block is hardware efficient than the multiplier block. Square of an operand is computed using the Dwandwa Yoga or Duplex method. Any number can be represented as
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Multiplier is a major block in designing digital systems. Several algorithms are reported in literature to implement fast multipliers. VEDIC multiplication algorithm is another option to implement an efficient multiplier. This work discuses the VEDIC multiplier. There are 3 methods to implement multiplication in VEDIC mathematics. Out of three, only one method is generic method
The impulse response of a Finite Impulse Response (FIR) filter is of finite duration as it settles to zero in finite time. In comparison to the Infinite Impulse Response (IIR) filters, there is no feedback in FIR filter. This feature makes the FIR filter always stable. Another important feature of FIR filter is that it
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K-means algorithm is very popular because of its simplicity. This is an iterative algorithm which tries to partition a dataset into K groups. K-means algorithm tries to group the similar data samples in a cluster in every iteration. This is carried out based on some formulas which computes the similarity between two vectors. This algorithm
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In our previous tutorial sequential circuits, many different clock divider circuits are introduced. Here in this tutorial, a basic architecture of a programmable clock divider is presented. Clock divider circuits have many use in frequency synthesizers. A basic circuit is presented below in Figure 1. The circuit is capable of dividing the input clock by
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In the previous tutorials, we have discussed about the fixed point architectures. Majority of FPGA based architectures are fixed point based. In the fixed point architectures, the number of bits reserved for integer and fractional part is fixed. Thus there is a limitation in representing wide range of numbers. This limitation results truncation error at
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The floating point to fixed point conversion is necessary to interface a floating processor to a fixed point implementation. So that there maintains a smooth transition from one type of architecture to another. The steps involved in this conversion are Concatenate the hidden bit and add leading zeros according to the fixed point length. Find
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Floating point comparison is similar to the comparison of two numbers in fixed point arithmetic as discussed in the post for combinational circuits. The same architecture can be used here also. Yet this architecture is discussed here to have clear idea about floating point comparison. The steps involving the comparison of two floating point numbers
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