In the previous tutorials, we have seen how to use Cadence INNOVUS GUI for placement and routing. But INNOVUS tool works better when used with scripts. It is convenient to use the script based placement and routing as numerous runs are needed to successfully verify an IC. This is also the industrial practice. In this […]
PnR using INNOVUS with scripts Read More »
In the previous three tutorials, we have learned how prepare the files which are needed to start the placement and routing using INNOVUS. In this tutorial, a basic tutorial on how to perform placement and routing using INNOVUS is given. This is a very fundamental and only covers the basic ideas and follows the tutorial
Placement and Routing using INNOVUS Read More »
In the previous tutorial on Placement and Routing using INNOVUS, we have seen how to open the tool and how to import all the files. In this tutorial, we will discuss how to prepare view definition file by performing Multi Mode Multi Corner (MMMC) analysis. MMMC analysis is very important to perform, so that the
MMMC file setup for PnR using INNOVUS Read More »
The previous tutorials [Tutorial 1, Tutorial 2] are on the simulation and synthesis of Verilog files. In addition to these we have also performed linting, code coverage, logic equivalence check, DFT, ATPG, power analysis and Timing analysis using CADENCE and SYNOPSYS tools. Till now we have not discussed anything about the step Placement and Routing
Placement and Routing for ASIC Read More »
