In our earlier tutorials [GENUS Synthesis With Constraints, GENUS Synthesis Without Constraints] on synthesis of Verilog files using Cadence Genus tool, we have seen how synthesis can be performed with or without timing constraints. But it is very painful to perform synthesis operation by executing commands one by one in the command prompt. Thus industry practice is to use the SCRIPT files for every major process like synthesis, logic equivalence checking or implementation. Here, we will discuss how to perform GENUS Synthesis using SCRIPTS.
The Tool Command Language (TCL) format is used to write the commands in a file that is understood by the tool. The command to run the GENUS Synthesis using SCRIPTS is
genus -legacy_ui -f genus_script.tcl
Here, example of two type of script file is given which are genus_script.tcl and genus_script_dft.tcl
genus_script.tcl – this file is written to synthesis the Verilog file IIR_LPF_direct1 which is implementation of IIR low pass filter. Here, in this file many sub-modules are present. Thus in the elaborate command we have to set the TOP Module which is IIR_LPF_direct1. Here, some of the comments are commented by # symbol, readers are advised to check function each commands.
set_attribute init_lib_search_path/home/guests/phd/shir_16/libraries
set_attribute init_hdl_search_path/home/guests/phd/shir_16/Synthesis
set_attribute library tsl18fs120_scl_ff.lib
read_hdl IIR_LPF_direct1.v
elaborate IIR_LPF_direct1 #Name of the Top Module
read_sdc /home/guests/phd/shir_16/libraries/IIR_LPF_direct1.sdc
#set_attribute syn_generic_effort medium
#set_attribute syn_map_effort medium
#set_attribute syn_opt_effort medium
#syn_generic
#syn_map
#syn_opt
set_attr tns_opto true
#set_attr boundary_opto 1
#set_attribute hdl_preserve_unused_register true
#set_attribute delete_unloaded_seqs false
#set_attribute optimize_constant_0_flops false
#set_attribute optimize_constant_1_flops false
#set_attribute prune_unsued_logic false
synthesize -to_mapped -effort medium
write_hdl > IIR_LPF_direct1.v
write_sdf > IIR_LPF_direct1.sdf
#write_sdf -timescale ns -nonegchecks -recrem split -edges check_edge > delays.sdf
write_sdc > IIR_LPF_direct1.sdc
report_units
report_units > design_units
report_gates
report_gates > design_gates
report_power
report_power > design_power
report_timing
report_timing > design_timing
report_qor
report_qor > design_qor
check_design
gui_showgenus_script_dft.tcl – This file synthesizes the IIR_LPF_direct1.v file with the MUX based scan chains which will be discussed later in the future posts.
set_attribute init_lib_search_path /home/guests/phd/shir_16/libraries
set_attribute init_hdl_search_path /home/guests/phd/shir_16/Synthesis_DFT
set_attribute library tsl18fs120_scl_ff.lib
read_hdl IIR_LPF_direct1.v
elaborate IIR_LPF_direct1
read_sdc /home/guests/phd/shir_16/libraries/IIR_LPF_direct1.sdc
set_attr dft_scan_style muxed_scan
set_attr dft_prefix dft_
define_shift_enable -name SE -active high -create_port SE
check_dft_rules
#set_attribute syn_generic_effort medium
syn_generic
set_attribute syn_map_effort medium
syn_map
set_attribute syn_opt_effort medium
syn_opt
check_dft_rules
set_attr dft_min_number_of_scan_chains 1 /designs/counter
define_scan_chain -name top_chain -sdi scan_in -sdo scan_out -create_ports
connect_scan_chains -auto_create_chains
syn_opt -incr
report_scan_chains
write_dft_atpg -library /home/guests/phd/shir_16/libraries/tsl18fs120_scl_ff.v
write_hdl > IIR_LPF_direct1_netlist_dft.v
write_sdc > IIR_LPF_direct1_sdc_dft.sdc
write_sdf -nonegchecks -edges check_edge -timescale ns -recrem split > IIR_LPF_direct1_dft.sdf
write_scandef > IIR_LPF_direct1_scanDEF.scandef
