The previous tutorials [Tutorial 1, Tutorial 2] are on the simulation and synthesis of Verilog files. In addition to these we have also performed linting, code coverage, logic equivalence check, DFT, ATPG, power analysis and Timing analysis using CADENCE and SYNOPSYS tools. Till now we have not discussed anything about the step Placement and Routing […]
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In the previous tutorials, we have discussed how to simulate or synthesize a design using Synopsys or Cadence. Static Timing Analysis is a very important step in designing an digital design for ASIC. This tutorial is on performing Static Timing Analysis using Cadence Tempus. 1. Open the terminal 2. Source the cadence.cshrc 3. In this
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Automatic Test Pattern Generation and Automatic Test Pattern Generator (ATPG) is an electronic design automation method/technology used to find an input (or test) sequence that, when applied to a digital circuit, enables automatic test equipment to distinguish between the correct circuit behavior and the faulty circuit behavior caused by defects. Earlier we presented a tutorial on ATPG for Combinational Circuits. This tutorial focuses on ATPG for sequential circuits
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This tutorial is in continuation with our previous tutorial on Genus Synthesis Without Constraints (Timing Constraints). The timing constraints are written in Synopsys Design Constraint (SDC) file. 1. Open the terminal and type csh 2. Source the cadence.cshrc. 3. In ASIC lab folder, make a new directory. In this, make design.v (in this example counter.v).
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Code coverage is a basic coverage type which is collected automatically. It tells you how well your HDL code has been exercised by your test bench. In other words, how thoroughly the design has been executed by the simulator using the tests used in the regression. Functional coverage measures how well the functionality of the
