ASIC Tutorials I

By DR. SHIRSHENDU ROY / 22nd June 2020 / ASIC

Here, we will discuss the tutorials on how to synthesize a Verilog code starting from simulation, syntax checking, code coverage using CADENCE EDA tool.

Basic Simulation on CADENCE
Linting
Code Coverage
Logic Equivalence Check
Genus Synthesis without Constraints
Genus Synthesis with Constraints
Genus Synthesis using Scripts
Static Timing Analysis using Cadence Tempus

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