ASIC TUTORIALS II
Synopsys Simulation and Synthesis ATPG for Combinational Circuits ATPG for Sequential circuits Power Analysis using Synopsys 00
Synopsys
Static Timing Analysis using Cadence Tempus
In the previous tutorials, we have discussed how to simulate or synthesize a design using Synopsys or Cadence. Static Timing Analysis is a very important step in designing an digital design for ASIC. This tutorial is on performing Static Timing Analysis using Cadence Tempus. 1. Open the terminal 2. Source the cadence.cshrc 3. In this
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ATPG for Combinational Circuits
Automatic Test Pattern Generation and Automatic Test Pattern Generator (ATPGA) is an electronic design automation method/technology used to find an input (or test) sequence that, when applied to a digital circuit, enables automatic test equipment to distinguish between the correct circuit behavior and the faulty circuit behavior caused by defects. This tutorial focuses on ATPG for combinational circuits using Synopsys Tetramax tool. 1. Open the terminal 2. Source
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Synopsys Simulation and Synthesis
Here, tutorial on simulation of Verilog file using Synopsys EDA tool is given. Also, synthesis using Deign Vision tool is also shown. The reader find this tutorial on Synopsys Simulation and Synthesis very useful. 1. Open the terminal 2. Source the synopsys.cshrc 3. Check whether the commands are working as below. Terminal will echo the
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