Sequential Circuits Welcome to your QUIZ on Sequential Circuits 1 Your Name Please Enter Your Email 1. In a negative edge triggered flip-flop, in order to have the output Q state 0, 0 and 1 in the next three successive clock pulses the J-K input states required would be respectively . 00,00 and 10 00,01 and 11 00,10 and 11 01,10 and 11 None 2. The initial state of MOD-16 down counter is 0110. After 37 clock pulses, the state of the counter will be. 1011 0110 0100 0001 None 3. Symmetrical square wave of time period 100 us can be obtained from square wave of time period 10 us by using a divide by-5 circuit divide by-2 circuit divide by-5 circuit followed by divide by-2 circuit a JK flip-flop None 4. T-flip-flop function is obtained from a JK flip-flop. If the flip-flop belongs to TTL family, the connections needed at the input must be. J=K=1 J=K=0 J=1 and K =0 J=0 and K =1 None 5. A ring counter consisting of five flip-flops will have 5 states 10 states 32 states Infinite states None 6. The 54 / 74164 chip is an 8-bit serial-input-parallel –output shift register. The clock is 1 MHz the time needed to shift an 8-bit binary number into chip is 1 us 2 us 8 us 16 us None 7. Minimum number of J-K flip-flops needed to construct a BCD counter is 2 3 4 5 None 8. The number of unused states in a 4-bit Johnson counter is 2 4 8 12 None 9. For the circuit shown below the counter state (Q1,Q0) follows the sequence 00, 01, 10, 11, 00, .. 00, 01, 10, 00, 01, .. 00, 01, 11, 00, 01, .. 00, 10, 11, 00, 10, .. None 10. Analyse the circuit shown below. Assume initial state is 00, determine what input sequence would lead to state 11? 1 - 1 1 - 0 0 - 0 State 11 is unreachable None 11. In the following figure 1010 is initially loaded in the register. After how many clock pulses the content of the shift register will be 1010 again. 3 7 11 15 None 12. An X-Y flip-flop, whose characteristic table is given below is to be implemented using J-K flip-flop. This can be done by making \[J=X, K = \bar{Y}\] \[J=\bar{X}, K = Y\] \[J=Y, K = \bar{X}\] \[J=\bar{Y}, K = X\] None 13. The J-K flip-flop shown below is initially reset, so that Q = 0. If a sequence of four clock pulses is then applied, with the J and K inputs as given in the figure. The resulting sequence of values that appear at the output Q starting with its initial state is given by 01011 01010 00110 00101 None 14. Which of the following flip-flop is used as a latch? J-K flip-flop R-S flip-flop T flip-flop D flip-flop None 15. The below circuit illustrates a typical application of the J-K flip-flops. What does this represent. A shift register A data storage device A frequency divider circuit A decoder circuit None 16. A 1ms pulse can be converted into a 10 ms pulse by using which one of the following? An astable multivibrator A mono stable multivibrator A bistable multivibrator A J-K flip-flop None 17. The characteristic equation of a J-K flip-flop is \[ Q_{N+1} = J\bar{Q_N} + \bar{K}Q_N \] \[ Q_{N+1} = J+ \bar{K}Q_N \] \[ Q_{N+1} = K\bar{Q_N} + \bar{J}Q_N \] \[ Q_{N+1} = K + \bar{J}Q_N \] None 18. The circuit shown below is of Mod-5 counter Mod-6 counter Mod-7 counter Mod-8 counter None 19. 12 MHz clock frequency is applied to a cascaded counter of Mod-3 counter, Mod-4 counter and Mod-5 counter. What is the lowest output frequency and Mod number . 200 KHz, 60 1 MHz, 60 3 MHz, 12 4 MHz, 12 None 20. What will be the content of the shift register shown below after 3 clock pulses? 0000 0101 1010 1111 None 21. The below shown J-K flip-flop is initially cleared. The output sequence at Q will be after 6 clock pulses 010001 011001 010010 010101 None 22. Total number of 1's in a 15-bit shift register is to be counted by clocking into a counter which is preset to 0. The counter must have which one of the following ? 4-bits 5-bits 3-bits 16-bits None 23. Output characteristic of T flip-flop is \[ Q^* = TQ + \bar{T}\bar{Q}\] \[ Q^* = T\bar{Q} + \bar{T}Q\] \[ Q^* = T + Q \] \[ Q^* = T\bar{Q}\] None 24. In the 3-bit shift register, to have content '000' again the number of clock cycles required would be 3 6 8 16 None 25. What is the maximum modulus number for a counter with 5 number of flip-flops ? 16 32 64 8 None 26. Number of flip-flops required to construct mod-10 counter will be 1 2 3 4 None 27. Number of flip-flops required to divide input frequency by 64? 2 4 5 6 None 28. How many illegitimate states a synchronous mod-6 counter has ? 3 2 1 0 None 29. R-S latch is a Combinational circuit Synchronous sequential Element 1 bit memory element 1 clock delay element None 30. A 0 to 6 counter consists of 3 flip-flops and a combination circuit of 2 input gates. The combination circuit consists of one AND gate one OR gate one AND gate and one OR gate two AND gates None 31. What will be the status of (Q1,Q0) after 3 clock cycles if the flip-flops are initially cleared. 10 01 00 11 None 32. The Race Around condition exists in J-K flip-flop when J=0, K=1 J=1, K=0 J=0, K=0 J=0, K=1 None 33. In a J-K flip-flop, the output Q is 1 and it does not change when a clock pulse is applied. The possible condition of J and K will be. (x is don't care) x and 0 x and 1 0 and x 1 and x None 34. What type of counter is shown here Syhnchronous Johnson Ring None None 35. Which of the following is not a characteristic of a flip-flop? The flip-flop is a bistable device with only two stable states The flip-flip has two input signals The flip-flip has two output signals The outputs are complement of each other None 36. which of the following statements is not correct ? A flip-flop is used to store 1-bit information. Race-around condition occurs in J-K flip-flop to store 2-bits of information. Master-Slave configuration is used in flip-flops to store 2-bits of information A transparent latch consists of a D-type flip-flop. None 37. Which type of flip-flop is realized in the following figure ? SR flip-flop J-K flip-flop T flip-flop D flip-flop None 38. If input frequency is 12 MHz then the output frequency is 24 KHz 12 KHz 6 KHz 3 KHz None Please fill in the comment box below. Time's up 00
