Verilog Code for 16-bit Floating Point Pipelined Divider


Product Specifications

  1. 16-bit Floating Point Divider
  2. Parallel and Pipelined
  3. 4-bits for Biased Exponent and 11-bits for Magnitude
  4. Structural Verilog Design
  5. Fixed point divider is 18-bit unsigned.
  6. Result is verified by simulation. FPGA implementation is not verified.

Divider is a very complex digital block to design and it consumes more hardware resources than the other arithmetic blocks. Now the implementation of divider block in floating point representation is even more critical. Here, a Verilog implementation of 16-bit floating point divider is presented. Here, 16-bit frame length is used to represent the floating point representation. Out of which 11-bits are used for magnitude part and 4-bits are used for biased exponent. Remaining 1-bit indicates the sign of the number. The divider is parallel and pipeline stages are inserted to achieve higher frequency of operation.


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