Design and implementation of square root block is as difficult as it is difficult to design a divider block. Here Verilog Code for 11-bit Floating Point Parallel Square Root Block is provided. Here, 1-bit is used to represent sign, 4-bits are used to represent the biased exponent and 6-bits are used for the magnitude part. This block is a parallel design and the fixed point square root is Non-restoring algorithm based.

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