Floating Point Square Root IP

$5.00

Features

  1. This is a Floating Point Square Root IP
  2. It can receive any data width but maximum width of mantissa is 31
  3. Fully parallel and pipelined
  4. Non-restoring technique based
  5. Fully tested on FPGA with ILA
  6. Latency is Flm/2 + 1 number of clock cycles.

Just like fixed point square root IP which was previously added, Floating Point Square Root IP computes square root of any floating point number. As mentioned previously that square root operation is complex and hardware expensive, we are offering this IP so that a researcher can use it in their design without any effort. Floating Point Square Root IP is based on the simple non-restoring technique as discussed earlier.

Floating point data format has three fields, sign (S), mantissa (M), and biased exponent (E). Most used data width (N) for floating point architectures are half precision (N =16, M =10), single precision (N=32, M = 23), and double precision (N = 64, M =52). Floating Point Square Root IP is designed such a way that it can take any data width and width of the mantissa also can be varied. But has some limitations. The width of the mantissa can take maximum value of 31. This means Floating Point Square Root IP does not support double precision square root computation. But in case FPGA application, double precision is hardly used.

Floating Point Square Root IP is tested on Xilinx XC7A35T-1FTG256 Artix 7 FPGA which has 50 MHZ onboard clock oscillator. Testing is carried out using Xilinx ILA. FPGA performance of this IP is shown below in a table.

Dynamic power consumption of this IP is computed as operating frequency of 200 MHz. This IP has two parameters, N and Flm. This IP is well suitable for any application and is fully parallel and pipelined. It has latency of (Flm/2 + 1) clock cycles.  This IP is designed with Verilog HDL and supported with AXI interface to be interfaced in SoC design.

 

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