Signed Fixed Point Multiplier IP

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This IP is designed to multiply two signed fixed point numbers. There is no pipeline stages are included in this IP. So it is a pure combinational circuit. Both data width and precision can be varied. This is different than the multiplier IP provided by the XILINX. It automatically adjusts the precision. For example, if data width is 16 and 10-bits are used for fraction then the output will also be of 16-bits and with 10-bits fraction.

The instructions on how to use this IP is given in the following link

Downloads – Digital System Design

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The major points about this IP are

  1. It is Verilog HDL based IP.
  2. It multiplies two signed numbers.
  3. Fixed point data can be multiplied by this multiplier.
  4. Precision and data-width both can be varied.
  5. A top module Verilog file is added so that the Verilog code can be used without using block design.
  6. The Verilog code is encrypted by XILINX.
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