Adder tree is a very important IP to process image, video or audio signals on FPGA device. Adder tree is generally used for matrix multiplications. Here, a general pipelined adder tree is designed which can except any number of inputs (M) and any data width (N). The adder tree is pipelined means that a register is placed between two adders. This way this block can be very useful to the designers.
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General Pipelined Adder Tree IP
$4.00
Adder tree is a very important IP to process image, video or audio signals on FPGA device. Adder tree is generally used for matrix multiplications. Here, a general pipelined adder tree is designed which can except any number of inputs (M) and any data width (N). The adder tree is pipelined means that a register is placed between two adders. This way this block can be very useful to the designers.
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