`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    14:45:40 05/03/2020 
// Design Name: 
// Module Name:    Vedic_cubic 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module Vedic_cube_4bit(a,s
    );
input [3:0] a;
output [15:0] s;
wire [4:0] s0,s5;
wire [2:0] s1,s3;
wire [3:0] s2,s4,s6,s7;
wire [8:0] s8,s9,s10,s11;
wire [10:0] s12,s13;
wire c1,c2,c3,c4;

//////// First stage ////////
////Compute y^3....
Vedic_cube_2bit m1(a[1:0],s0);
////Compte 3x /////
assign {s1[2:1],s1[0]} = {a[3:2],1'b0};
ha ad1(s1[0],a[2],s2[0],c1);
fa ad2(s1[1],a[3],c1,s2[1],c2);
ha ad3(s1[2],c2,s2[2],s2[3]);
////Compte 3y /////
assign {s3[2:1],s3[0]} = {a[1:0],1'b0};
ha ad4(s3[0],a[0],s4[0],c3);
fa ad5(s3[1],a[1],c3,s4[1],c4);
ha ad6(s3[2],c4,s4[2],s4[3]);
////Compute x^3 .....
Vedic_cube_2bit m2(a[3:2],s5);
////Compute x^2...
Vedic_mul_2bit m3(a[3:2],a[3:2],s6);
////Compute y^2...
Vedic_mul_2bit m4(a[1:0],a[1:0],s7);

//////// Second stage ////////
////Multiply 3x and y^2.....
Vedic_mul_4bit m5(s2,s7,s8);
////Multiply 3y and x^2.....
Vedic_mul_4bit m6(s4,s6,s9);

//////// 3rd stage ////////
//// Add y^3 and 3xy^2
RCA8 rc1({6'b000000,s0[4:2]},s8,1'b0,s10,c5);
//// Add y^3 and 3x^2y
RCA8 rc2({2'b00,s9[8:2]},{4'b0000,s5},1'b0,s11,c6);
assign s12 = {c6,s11,s9[1:0]};

//////// Fourth stage ////////
RCA11 rc3(s12,{3'b000,c5,s10[8:2]},1'b0,s13,c7);
assign s = {c7,s13,s10[1:0],s0[1:0]};
endmodule

module Vedic_cube_2bit(a,s
    );
input [1:0] a;
output [4:0] s;
wire s0,s5;
wire [1:0] s1,s2,s3,s4,s6,s7;
wire c1;

////Compute y^3....
assign s0 = a[0];
////Compute 3x....
assign {s1[1],s1[0]} = {a[1],1'b0};
assign {s2[1],s2[0]} = {s1[1],a[1]};
////Compute 3y....
assign {s3[1],s3[0]} = {a[0],1'b0};
assign {s4[1],s4[0]} = {s3[1],a[0]};
////Compute x^3....
assign s5 = a[1];
////Compute 3x^2y....
assign s6[0] = s2[0] & a[0];
assign s6[1] = s2[1] & a[0];
////Compute 3xy^2....
assign s7[0] = s4[0] & a[1];
assign s7[1] = s4[1] & a[1];
//////addition......
assign s[0] = s0;
assign s[1] = s7[0];
ha m1(s7[1],s6[0],s[2],c1);
fa m2(s6[1],s5,c1,s[3],s[4]);
endmodule
module Vedic_square_8bit(a,s);
input [7:0] a;
output [17:0] s;
wire [8:0] s1,s2,s3,s4,s5,s6;
wire c1,c2,c3;
Vedic_square_4bit m1(a[3:0],s1);
Vedic_square_4bit m2(a[7:4],s2);
Vedic_mul_4bit m3(a[7:4],a[3:0],s3);
	
lsh1_8bit sh(s3[7:0],s4,c1);
RCA8 ad2(s4,{5'b0000,s1[7:4]},1'b0,s5,c2);
RCA8 ad3(s2,{3'b000,c1&c2,c1^c2,s5[7:4]},1'b0,s6,c3);	 
assign s = {c3,s6,s5[3:0],s1[3:0]};
endmodule

module Vedic_square_4bit(a,s);
input [3:0] a;
output [8:0] s;
wire [3:0] s1,s2,s3,s4,s5,s6;
wire c1,c2,c3;
Vedic_mul_2bit m1(a[1:0],a[1:0],s1);
Vedic_mul_2bit m2(a[3:2],a[3:2],s2);
Vedic_mul_2bit m3(a[3:2],a[1:0],s3);
	
lsh1 sh(s3,s4,c1);
RCA ad2(s4,{1'b0,1'b0,s1[3:2]},1'b0,s5,c2);
RCA ad3(s2,{1'b0,c1|c2,s5[3:2]},1'b0,s6,c3);	 
assign s = {c3,s6,s5[1:0],s1[1:0]};
endmodule

module Vedic_mul_8bit(a,b,s
    );
input [7:0] a,b;
wire [8:0] s1,s2,s3,s4,s5,s6,s7;
output [17:0] s;
wire c1,c2,c3;	
Vedic_mul_4bit m1(a[3:0],b[3:0],s1);
Vedic_mul_4bit m2(a[3:0],b[7:4],s2);
Vedic_mul_4bit m3(a[7:4],b[3:0],s3);
Vedic_mul_4bit m4(a[7:4],b[7:4],s4);

RCA8 ad1(s2,s3,1'b0,s5,c1);	
RCA8 ad2({s5},{5'b00000,s1[7:4]},1'b0,s6,c2);
RCA8 ad3(s4,{3'b000,1'b0,c1|c2,s6[7:4]},1'b0,s7,c3);	 
assign s = {c3,s7,s6[3:0],s1[3:0]};
endmodule
module Vedic_mul_4bit(a,b,s
    );	
input [3:0] a,b;
output [8:0] s;
wire [3:0] s1,s2,s3,s4,s5,s6,s7;
wire c1,c2,c3;	 
Vedic_mul_2bit m1(a[1:0],b[1:0],s1);
Vedic_mul_2bit m2(a[1:0],b[3:2],s2);
Vedic_mul_2bit m3(a[3:2],b[1:0],s3);
Vedic_mul_2bit m4(a[3:2],b[3:2],s4);

RCA ad1(s2,s3,1'b0,s5,c1);	
RCA ad2({s5},{1'b0,1'b0,s1[3:2]},1'b0,s6,c2);
RCA ad3(s4,{1'b0,c1|c2,s6[3:2]},1'b0,s7,c3);	 
assign s = {c3,s7,s6[1:0],s1[1:0]};
endmodule

module Vedic_mul_2bit(a,b,s
    );
input [1:0] a,b;
output [3:0] s;
wire a1b1,a0b0,a0b1,a1b0,c1;
assign a1b1 = a[1] & b[1];
assign a1b0 = a[1] & b[0];
assign a0b1 = a[0] & b[1];
assign a0b0 = a[0] & b[0];
ha m1(a0b1,a1b0,s[1],c1);
ha m2(a1b1,c1,s[2],s[3]);
assign s[0] = a0b0;
endmodule

module ha(
  input a,b,
  output sum,co
    );
assign sum = a^b;
assign co = a&b;
endmodule

module fa(a,b,cin,sum,co);
input a,b,cin;
output sum,co; 

assign sum = a ^ b ^ cin;
assign co = (a&b) | (b&cin) | (a&cin);

endmodule

module RCA8(a,b,cin,sum,co);
input [8:0] a,b;
input cin;
output [8:0] sum;
output co;
wire c1,c2,c3,c4,c5,c6,c7,c8;
fa m1(a[0],b[0],cin,sum[0],c1);
fa m2(a[1],b[1],c1,sum[1],c2);
fa m3(a[2],b[2],c2,sum[2],c3);
fa m4(a[3],b[3],c3,sum[3],c4);
fa m5(a[4],b[4],c4,sum[4],c5);
fa m6(a[5],b[5],c5,sum[5],c6);
fa m7(a[6],b[6],c6,sum[6],c7);
fa m8(a[7],b[7],c7,sum[7],c8);
fa m9(a[8],b[8],c8,sum[8],co);
endmodule

module RCA11(a,b,cin,sum,co);
input [10:0] a,b;
input cin;
output [10:0] sum;
output co;
wire c1,c2,c3,c4,c5,c6,c7,c8;
fa m1(a[0],b[0],cin,sum[0],c1);
fa m2(a[1],b[1],c1,sum[1],c2);
fa m3(a[2],b[2],c2,sum[2],c3);
fa m4(a[3],b[3],c3,sum[3],c4);
fa m5(a[4],b[4],c4,sum[4],c5);
fa m6(a[5],b[5],c5,sum[5],c6);
fa m7(a[6],b[6],c6,sum[6],c7);
fa m8(a[7],b[7],c7,sum[7],c8);
fa m9(a[8],b[8],c8,sum[8],c9);
fa m10(a[9],b[9],c9,sum[9],c10);
fa m11(a[10],b[10],c10,sum[10],co);
//fa m12(a[11],b[11],c8,sum[8],co);

endmodule

module RCA(a,b,cin,sum,co);
input [3:0] a,b;
input cin;
output [3:0] sum;
output co;
wire c1,c2,c3;
fa m1(a[0],b[0],cin,sum[0],c1);
fa m2(a[1],b[1],c1,sum[1],c2);
fa m3(a[2],b[2],c2,sum[2],c3);
fa m4(a[3],b[3],c3,sum[3],co);
endmodule

module lsh1(a,b,c);
    input [3:0] a;
    output [3:0] b;
	 output c;
assign {b[3:0]}= {a[2:0],1'b0};
assign c = a[3];
endmodule

module lsh1_8bit(a,b,c);
    input [7:0] a;
    output [7:0] b;
	 output c;
assign {b[7:0]}= {a[7:0],1'b0};
assign c = a[7];
endmodule