module srff(S,R,clk,reset,q,qb);
output reg q,qb ;
input S,R,clk,reset;
initial begin q=1'b0; qb =1'b1; end
always @ (posedge clk) 
 if (reset) begin
  q <= 0;
  qb <= 1;
 end
 else begin
  if (S!=R) begin
   q <= S;
   qb <= R;
  end
  else if (S==1 && R==1) begin
   q <= 1'bZ;
   qb <= 1'bZ;
  end
 end 
endmodule

module jk(q,qb,j,k,reset,clk);
output reg q,qb;
input j,k,clk,reset;
initial begin q=1'b0; qb=1'b1; end
always @ (posedge clk)
if(reset)
begin
q = 1'b0;
qb = 1'b1;
end
else
case({j,k})
{1'b0,1'b0}: begin q=q; qb=qb; end
{1'b0,1'b1}: begin q=1'b0; qb=1'b1; end
{1'b1,1'b0}: begin q=1'b1; qb=1'b0; end
{1'b1,1'b1}: begin q=~q; qb=~qb; end
endcase
endmodule

module tff(q,reset,clk,t);
output reg q;
input t,reset,clk;
initial begin q=1'b0; end
always @ (posedge clk)
if (reset)
q <= 1'b0;
else if (t)
q= ~q;
else 
q = q;
endmodule

module dff_struct(q,qb,d,reset,ce,clk);
output q,qb;
input d,reset,ce,clk;
wire t1,t2,d1,d2,d3;
wire clk1,clk2,clk3,posedge;
assign #0.2 clk1 = ~clk;
assign #0.2 clk2 = ~clk1;
assign #0.2 clk3 = ~clk2;
assign d1 = ~ce & q & ~reset;
assign d2 = ce & d & ~reset;
assign d3 = d1 |d2 ;
assign posedge = clk3 & clk;
assign t1 = ~(d3 & posedge) ;
assign t2 = ~(~d3 & posedge) ;
assign q = ~(t1 & qb);
assign qb = ~(t2 & q );
endmodule

module dff(q,reset,clk,d);
output reg q;
input reset,d,clk;
initial begin q=1'b0; end
always @ (posedge clk)
if (reset)
q <= 1'b0;
else 
q<=d;
endmodule

module msd(d,clk,reset,q);
output q ;
input d,clk,reset ;
wire q1,clkb;
assign clkb = ~clk ;
dff m1(q1,d,reset,clk);  
dff m2(q,q1,reset,clkb); 
endmodule

Shift Registers........

module pipo(q,reset,clk,d);
input clk,reset;
input [3:0] d;
output [3:0] q;
dff m1(q[0],reset,clk,d[0]);
dff m2(q[1],reset,clk,d[1]);
dff m3(q[2],reset,clk,d[2]);
dff m4(q[3],reset,clk,d[3]);
endmodule

module piso(q,reset,clk,s,d);
input clk,reset,s;
input [3:0] d;
output q;
wire t1,t2,t3,t4,t5,t6,t7;
mux_df mx1(1'b0,d[0],s,t1);
dff m1(t2,reset,clk,t1);
mux_df mx2(t2,d[1],s,t3);
dff m2(t4,reset,clk,t3);
mux_df mx3(t4,d[2],s,t5);
dff m3(t6,reset,clk,t5);
mux_df mx4(t6,d[3],s,t7);
dff m4(q,reset,clk,t7);
endmodule

module siso(q,reset,clk,d);
input clk,reset;
input d;
output q;
wire t1,t2,t3;
dff m1(t1,reset,clk,d);
dff m2(t2,reset,clk,t1);
dff m3(t3,reset,clk,t2);
dff m4(q,reset,clk,t3);
endmodule

module sipo(q0,q1,q2,q3,reset,clk,d);
input clk,reset;
input d;
output q0,q1,q2,q3;
dff m1(q0,reset,clk,d);
dff m2(q1,reset,clk,q0);
dff m3(q2,reset,clk,q1);
dff m4(q3,reset,clk,q2);
endmodule

Counters...............

module loadcntup(out,data,load,en,reset,clk,tc,lmt);
output reg[3:0] out;
output reg tc;
input [3:0] data,lmt;
input load, en, clk,reset;
initial begin out=4'b00000;
tc=0; end
always @(posedge clk)
if (reset) begin
  out <= 4'b0 ;
end else if (en) begin
if (load)
  out <= data;
  else
  out <= out + 4'b0001;
end
always @(posedge clk)
if (out ==lmt)
tc<=1;
else tc<=0;
endmodule 

module loadcnt_up(q,b,load,en,reset,clk,tc,lmt);
input clk,load,en,reset;
input [3:0] b,lmt;
output [3:0] q;
output tc;
wire a1,a2,a3,t1,t2,t3,t4,en1;
wire [3:0] d;
assign d[0] = ~q[0];
assign d[1] = q[1]^q[0];
assign d[2] = q[2]^(q[1]&q[0]);
assign d[3] = q[3]^(q[2]&q[1]&q[0]);
mux_df m1(d[0],b[0],load,t1);
dff1 d1(q[0],clk,reset,t1,en1);
mux_df m2(d[1],b[1],load,t2);
dff1 d2(q[1],clk,reset,t2,en1);
mux_df m3(d[2],b[2],load,t3);
dff1 d3(q[2],clk,reset,t3,en1);
mux_df m4(d[3],b[3],load,t4);
dff1 d4(q[3],clk,reset,t4,en1);
assign en1 = load | en;
assign a1 = q[0] ~^ lmt[0];
assign a2 = q[1] ~^ lmt[1];
assign a3 = q[2] ~^ lmt[2];
assign a4 = q[3] ~^ lmt[3];
assign tc = a1 & a2 & a3 & a4;
endmodule

module loadcnt_dn(q,b,load,en,reset,clk,tc,lmt);
	 input clk,load,en;
wire [3:0] d;
input [3:0] b,lmt;
wire a1,a2,a3,t1,t2,t3,t4,en1;
output [3:0] q;
output tc;
assign d[0] = ~q[0];
assign d[1] = q[1] ^ ~q[0];
assign d[2] = q[2] ^  ( ~q[1] & ~q[0]);
assign d[3] = q[3] ^  ( ~q[2] & ~q[1] & ~q[0]);
mux_df m1(d[0],b[0],load,t1);
dff1 d1(q[0],clk,reset,t1,en1);
mux_df m2(d[1],b[1],load,t2);
dff1 d2(q[1],clk,reset,t2,en1);
mux_df m3(d[2],b[2],load,t3);
dff1 d3(q[2],clk,reset,t3,en1);
mux_df m4(d[3],b[3],load,t4);
dff1 d3(q[3],clk,reset,t4,en1);
assign en1 = load | en;
assign a1 = q[0] ~^ lmt[0];
assign a2 = q[1] ~^ lmt[1];
assign a3 = q[2] ~^ lmt[2];
assign a4 = q[3] ~^ lmt[3];
assign tc = a1 & a2 & a3 & a4;
endmodule

4-bit PN sequence Generation using LFSR

module PN_Seq_Gen(clk,reset,s,pn,d);
input clk,reset,s;
output pn;
input [3:0] d;
wire t1,t2,t3,t4,t5,t6,t7,t8,t9;
assign t1 = t3 ^ t9;
mux_df mx1(t1,d[0],s,t2);
dff m1(t3,reset,clk,t2);
mux_df mx2(t3,d[1],s,t4);
dff m2(t5,reset,clk,t4);
mux_df mx3(t5,d[2],s,t6);
dff m3(t7,reset,clk,t6);
mux_df mx4(t7,d[3],s,t8);
dff m4(t9,reset,clk,t8);
assign pn = t3^t5^t9;
endmodule

////////Clock Division...............
Approach 1

module clk_div1(clk,q0,q1,q2);
input clk;
output q0,q1,q2;
parameter reset = 1'b0;
dff m1(q0,reset,clk,~q0);
dff m2(q1,reset,q0,~q1);
dff m3(q2,reset,q1,~q2);
endmodule

Approach 2

module clk_div(clk,q0,q1,q2);
input clk;
output q0,q1,q2;
parameter t = 1'b1;
parameter reset = 1'b0;
tff m1(q0,reset,clk,t);
tff m2(q1,reset,q0,t);
tff m3(q2,reset,q1,t);
endmodule

Approach 3
Using Counter.....

Clock division by other than power of 2

Clock divide by 3 by Mod 3 counter

module clk_div_3(clk_out,clk,reset);
input clk,reset;
output clk_out;
wire t1,clkb,q0,q1,q2;
assign clkb = ~clk;
assign t1 = ~q0 & ~q1;
dff m1(q0,reset,clk,t1);
dff m2(q1,reset,clk,q0);
dff m3(q2,reset,clkb,q1);
assign clk_out = q2 | q1;
endmodule

A general Approach by Loadable Counter.........

module clk_div3(clk_out,clk,reset,en);
input clk,reset,en;
output clk_out;
wire [3:0] q;
wire clkb,q4,tc;
assign clkb = ~clk;
parameter lmt = 4'b0010;
parameter data = 4'b0000;
loadcnt_up cnt(q,data,tc,en,reset,clk,tc,lmt);
dff m3(q4,reset,clkb,q[1]);
assign clk_out = q[1] | q4;
endmodule

module clk_div5(clk_out,clk,reset,en);
input clk,reset,en;
output clk_out;
wire [3:0] q;
wire clkb,q4,tc;
assign clkb = ~clk;
parameter lmt = 4'b0100;
parameter data = 4'b0000;
loadcnt_up cnt(q,data,tc,en,reset,clk,tc,lmt);
dff m3(q4,reset,clkb,q[1]);
assign clk_out = q[2] | q4;
endmodule

module clk_div6(clk_out,clk,reset,en);
input clk,reset,en;
output clk_out;
wire [3:0] q;
wire clkb,q4,tc;
assign clkb = ~clk;
parameter lmt = 4'b0101;
parameter data = 4'b0000;
loadcnt_up cnt(q,data,tc,en,reset,clk,tc,lmt);
dff m3(q4,reset,clk,q[0]);
assign clk_out = q[1] | (q[0] & ~ q[2]);
endmodule

module clk_div7(clk_out,clk,reset,en);
input clk,reset,en;
output clk_out;
wire [3:0] q;
wire clkb,q4,tc;
assign clkb = ~clk;
parameter lmt = 4'b0110;
parameter data = 4'b0000;
loadcnt_up cnt(q,data,tc,en,reset,clk,tc,lmt);
dff m3(q4,reset,clkb,q[2]);
assign clk_out = q[2] | q4;
endmodule

module clk_div9(clk_out,clk,reset,en);
input clk,reset,en;
output clk_out;
wire [3:0] q;
wire clkb,q4,tc;
assign clkb = ~clk;
parameter lmt = 4'b1000;
parameter data = 4'b0000;
loadcnt_up cnt(q,data,tc,en,reset,clk,tc,lmt);
dff m3(q4,reset,clkb,q[2]);
assign clk_out = q[2] | q4;
endmodule

module clk_div10(clk_out,clk,reset,en);
input clk,reset,en;
output clk_out;
wire [3:0] q;
wire clkb,q4,tc;
assign clkb = ~clk;
parameter lmt = 4'b1001;
parameter data = 4'b0000;
loadcnt_up cnt(q,data,tc,en,reset,clk,tc,lmt);
dff m3(q4,reset,clk,q[2]);
assign clk_out = q[3] | q4;
endmodule

module clk_div11(clk_out,clk,reset,en);
input clk,reset,en;
output clk_out;
wire [3:0] q;
wire t1,clkb,q4,tc;
assign clkb = ~clk;
parameter lmt = 4'b1010;
parameter data = 4'b0000;
loadcnt_up cnt(q,data,tc,en,reset,clk,tc,lmt);
assign t1 = ~q[3] & ~q[2] & q[1];
dff m3(q4,reset,clkb,t1);
assign clk_out = q[2] | q4;
endmodule

module clk_div12(clk_out,clk,reset,en);
input clk,reset,en;
output clk_out;
wire [3:0] q;
wire t1,clkb,tc;
assign clkb = ~clk;
parameter lmt = 4'b1011;
parameter data = 4'b0000;
loadcnt_up cnt(q,data,tc,en,reset,clk,tc,lmt);
assign t1 = (q[2] & q[1]);
assign clk_out = q[3] | t1;
endmodule

module clk_div13(clk_out,clk,reset,en);
input clk,reset,en;
output clk_out;
wire [3:0] q;
wire t1,clkb,q4,tc;
assign clkb = ~clk;
parameter lmt = 4'b1100;
parameter data = 4'b0000;
loadcnt_up cnt(q,data,tc,en,reset,clk,tc,lmt);
assign t1 = (q[2] & q[1]);
dff m4(q4,reset,clkb,t1);
assign clk_out = q[3] | q4;
endmodule

module clk_div14(clk_out,clk,reset,en);
input clk,reset,en;
output clk_out;
wire [3:0] q;
wire t1,clkb,q4,tc;
assign clkb = ~clk;
parameter lmt = 4'b1101;
parameter data = 4'b0000;
loadcnt_up cnt(q,data,tc,en,reset,clk,tc,lmt);
assign t1 = (q[2] & q[1]);
dff m4(q5,reset,clk,t1);
assign clk_out = q[3] | q5;
endmodule

module clk_div15(clk_out,clk,reset,en);
input clk,reset,en;
output clk_out;
wire [3:0] q;
wire t1,clkb,q4,tc;
assign clkb = ~clk;
parameter lmt = 4'b1110;
parameter data = 4'b0000;
loadcnt_up cnt(q,data,tc,en,reset,clk,tc,lmt);
assign t1 = (q[2] & q[1] & q[0]);
dff m4(q4,reset,clkb,t1);
assign clk_out = q[3] | q4;
endmodule