mem_read.v

`timescale 1ns / 1ps

module mem_read(C1,ada,clk);
    input [9:0] ada;
	 input clk;
    integer of0;
    output reg [17:0] C1;
    reg [17:0] A1;
	 reg [17:0] b1 [1023:0];
	 integer j;
	 initial begin
	 of0=$fopen("input_vector.txt","r"); 
	 for (j=0;j<=1023;j=j+1)
	 begin 
        $fscanf(of0,"%d\n",A1); 
         #1;
        b1[j] = A1;
    end 
	 $fclose(of0);
	 end 
    always @ (posedge clk)
    begin 
	 C1 = b1[ada];
	 end
endmodule


Test_bench

`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   14:19:13 12/30/2018
// Design Name:   mem_read1
// Module Name:   D:/xilinx_simulation/blog/mem_read_tb.v
// Project Name:  blog
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: mem_read1
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module mem_read_tb;

	// Inputs
	reg [9:0] ada;
	reg clk;

	// Outputs
	wire [17:0] C1;

	// Instantiate the Unit Under Test (UUT)
	mem_read uut (
		.C1(C1), 
		.ada(ada), 
		.clk(clk)
	);
always #5 clk = ~clk;
	initial begin
		// Initialize Inputs
		ada = 0;
		clk = 0;

		// Wait 100 ns for global reset to finish
		#104.9;
        ada = 'd0;
		  #10;
		  ada = 'd1;
		  #10;
		  ada = 'd2;
		  #10;
		  ada = 'd3;
		  #10;
		// Add stimulus here

	end
      
endmodule



memwrite.v

`timescale 1ns / 1ps
module mem_write(A,en,clk);
    integer of0;
    input [17:0] A ;
	 input en,clk;
	 integer j;
	 initial begin j = 0; end
	 always @(posedge clk)
	 begin 
	 if (en)
	      begin
	 of0=$fopen("output_vector.txt","w");
	   for (j=0;j<=4;j=j+1)
  	      begin
	 $fdisplay(of0,"%d\n",A); 
	 #10;
	      end
		   end
	 else
	 $fclose(of0);
	 end
endmodule


Testbench

`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   14:29:05 12/30/2018
// Design Name:   mem_write
// Module Name:   D:/xilinx_simulation/blog/mem_wr_tb.v
// Project Name:  blog
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: mem_write
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module mem_wr_tb;

	// Inputs
	reg [17:0] A;
	reg en;
	reg clk;

	// Instantiate the Unit Under Test (UUT)
	mem_write uut (
		.A(A), 
		.en(en), 
		.clk(clk)
	);
always #5 clk = ~clk;
	initial begin
		// Initialize Inputs
		A = 0;
		en = 1;
		clk = 0;

		// Wait 100 ns for global reset to finish
		#104.9;
		en = 1;
       A = 'd0; 
		 #10;
		   A = 'd1; 
		 #10;
		 
		   A = 'd2; 
		 #10;
		 
		   A = 'd3; 
		 #10;
		 
		   A = 'd4; 
		 #10;
		 
		   A = 'd5; 
		 en = 0;
		 
		 
		// Add stimulus here

	end
      
endmodule