`timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// // Company: // Engineer: // // Create Date: 13:23:21 07/08/2018 // Design Name: // Module Name: Carryinc // Project Name: // Target Devices: // Tool versions: // Description: // // Dependencies: // // Revision: // Revision 0.01 - File Created // Additional Comments: // ////////////////////////////////////////////////////////////////////////////////// module Carryselectad(a,b,s,cout,c0); input [7:0] a,b; output [7:0] s; output cout; input c0; wire [3:0] s1,s2,s3,s4; wire c1,cout1,cout2,cout3,cout4; CLA4 cla1(a[3:0],b[3:0],s1[3:0],cout1,1'b0,,,,,,,,); CLA4 cla2(a[3:0],b[3:0],s2[3:0],cout2,1'b1,,,,,,,,); CLA4 cla3(a[7:4],b[7:4],s3[3:0],cout3,1'b0,,,,,,,,); CLA4 cla4(a[7:4],b[7:4],s4[3:0],cout4,1'b1,,,,,,,,); mux_df mx1(cout1,cout2,c0,c1); mux4_4_1 mx2(s1,s2,c0,s[3:0]); mux_df mx3(cout3,cout4,c1,cout); mux4_4_1 mx4(s3,s4,c1,s[7:4]); endmodule