`timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// // Company: // Engineer: // // Create Date: 19:38:55 07/21/2018 // Design Name: // Module Name: cond_sum_add // Project Name: // Target Devices: // Tool versions: // Description: // // Dependencies: // // Revision: // Revision 0.01 - File Created // Additional Comments: // ////////////////////////////////////////////////////////////////////////////////// module cond_sum_add(a,b,c0,cout,s ); input [3:0] a,b; output [3:0] s; input c0; output cout; wire c1,c2,c3,c4,c5,c6,c7,c23,c670,c671; wire s1,s2,s3,s4,s5,s6,s670,s671; fa m1(a[0],b[0],c0,s[0],c1,); fa m2(a[1],b[1],1'b0,s1,c2,); fa m3(a[1],b[1],1'b1,s2,c3,); fa m4(a[2],b[2],1'b0,s3,c4,); fa m5(a[2],b[2],1'b1,s4,c5,); fa m6(a[3],b[3],1'b0,s5,c6,); fa m7(a[3],b[3],1'b1,s6,c7,); mux_df mx1(c2,c3,c1,c23); mux_df mx2(s1,s2,c1,s[1]); mux_df mx3(c6,c7,c4,c670); mux_df mx4(s5,s6,c4,s670); mux_df mx5(c6,c7,c5,c671); mux_df mx6(s5,s6,c5,s671); mux_df mx7(c670,c671,c23,cout); mux_df mx8(s3,s4,c23,s[2]); mux_df mx9(s670,s671,c23,s[3]); endmodule module fa(a,b,cin,sum,co,t1); input a,b,cin; output sum,co,t1; wire t1,t2; ha X1(a,b,t1,t2); ha X2(cin,t1,sum,t4); assign co = t2 | t4; endmodule module mux_df( input a,b,s, output y ); wire sbar; assign y = (a&sbar)|(s&b); assign sbar = ~s; endmodule