`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    13:37:58 07/08/2018 
// Design Name: 
// Module Name:    Carryslct 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module Carryincadder(a,b,s,cout,c0);
input [7:0] a,b;
input c0;
output [7:0] s;
output cout;
wire [3:0] s1;
wire p0,p1,p2,p3,p4,p5,p6,p7,g1,g2,g3,g4,g5,g6,g7,g8;
wire cout1,cout2;
wire c1,c2,c3,c4;
CLA4 cla1(a[3:0],b[3:0],s[3:0],cout1,c0,p0,p1,p2,p3,g0,g1,g2,g3);
CLA4 cla2(a[7:4],b[7:4],s1[3:0],cout2,1'b0,p4,p5,p6,p7,g4,g5,g6,g7);
ha h1(cout1,s1[0],s[4],c1);
ha h2(c1,s1[1],s[5],c2);
ha h3(c2,s1[2],s[6],c3);
ha h4(c3,s1[3],s[7],c4);
assign cout = c4 | cout2;
endmodule


module CLA4(a,b,s,cout,c0,p0,p1,p2,p3,g0,g1,g2,g3);
input [3:0] a,b;
output [3:0] s;
output cout;
input c0;
output p0,p1,p2,p3;
output g0,g1,g2,g3;
wire c1,c2,c3,c4;
ha X1(a[0],b[0],p0,g0);
ha X2(a[1],b[1],p1,g1);
ha X3(a[2],b[2],p2,g2);
ha X4(a[3],b[3],p3,g3);
assign c1 = g0 | p0&c0;
assign c2 = g1 | p1&g0 | p1&p0&c0;
assign c3 = g2 | p2&g1 | p2&p1&g0 | p2&p1&p0&c0;
assign c4 = g3 | p3&g2 | p3&p2&g1 | p3&p2&p1&p0&c0;
assign s[0] = p0 ^ c0;
assign s[1] = p1 ^ c1;
assign s[2] = p2 ^ c2;
assign s[3] = p3 ^ c3;
assign cout = c4;
endmodule


module ha(
  input a,b,
  output sum,co
    );
assign sum = a^b;
assign co = a&b;
endmodule