`timescale 1ns / 1ps
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// Company: 
// Engineer: 
// 
// Create Date:    22:10:20 07/21/2018 
// Design Name: 
// Module Name:    BCD_add 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module BCD_add(a,b,s,cin,cout
    );
input [3:0] a,b;
output [3:0] s;
input cin;
output cout;
wire t1,t2,t3,co,c1,c2;	
wire [3:0] s1; 
RCA add(a,b,cin,s1,co);
assign t1 = s1[1] | s1[2];
assign t2 = s1[3] & t1;
assign t3 = co | t2;
ha m1(s1[1],t3,s[1],c1);
fa m2(s1[2],t3,c1,s[2],c2,);
ha m3(s1[3],c2,s[3],cout);
assign s[0] = s1[0];
endmodule