MEALY WITHOUT OVERLAP module melfsm(din, reset, clk, y); input din; input clk; input reset; output reg y; reg [1:0] cst, nst; parameter S0 = 2'b00, //all state S1 = 2'b01, S2 = 2'b10, S3 = 2'b11; always @(cst or din) begin case (cst) S0: if (din == 1'b1) begin nst = S1; y=1'b0; end else begin nst = cst; y=1'b0; end S1: if (din == 1'b0) begin nst = S2; y=1'b0; end else begin y=1'b0; nst = cst; end S2: if (din == 1'b1) begin nst = S3; y=1'b0; end else begin nst = S0; y=1'b0; end S3: if (din == 1'b0) begin nst = S0; y=1'b1; end else begin nst = S1; y=1'b0; end default: nst = S0; endcase end always@(posedge clk) begin if (reset) cst <= S0; else cst <= nst; end endmodule TESTBENCH module mealy_tb; // Inputs reg din; reg reset; reg clk; // Outputs wire y; // Instantiate the Unit Under Test (UUT) melfsm uut ( .din(din), .reset(reset), .clk(clk), .y(y) ); always #10 clk = ~clk; initial begin // Initialize Inputs din = 0; clk = 0; reset = 0; #91; din = 1; #20; din = 1; #20; din = 0; #20; din = 1; #20; din = 0; #20; din = 0; #20; din = 1; #20; din = 0; #20; din = 1; #20; din = 0; #20; // Add stimulus here end endmodule MEALY WITH OVERLAP module melfsmolp(din, reset, clk, y); output reg y; input din; input clk; input reset; reg [1:0] cst, nst; parameter S0 = 2'b00, S1 = 2'b01, S2 = 2'b10, S3 = 2'b11; always @(cst or din) begin case (cst) S0: if (din == 1'b1) begin nst = S1; y=1'b0; end else begin nst = cst; y=1'b0; end S1: if (din == 1'b0) begin nst = S2; y=1'b0; end else begin nst = cst; y=1'b0; end S2: if (din == 1'b1) begin nst = S3; y=1'b0; end else begin nst = S0; y=1'b0; end S3: if (din == 1'b0) begin nst = S2; y=1'b1; end else begin nst = S1; y=1'b0; end default: nst = S0; endcase end always@(posedge clk) begin if (reset) cst <= S0; else cst <= nst; end endmodule MOORE WITHOUT OVERLAP module morfsm(din, reset, clk, y); output reg y; input din; input clk; input reset; reg [2:0] cst, nst; parameter S0 = 3'b000, S1 = 3'b001, S2 = 3'b010, S3 = 3'b100, S4 = 3'b101; always @(cst or din) begin case (cst) S0: if (din == 1'b1) begin nst = S1; y=1'b0; end else begin nst = cst; y=1'b0; end S1: if (din == 1'b0) begin nst = S2; y=1'b0; end else begin nst = cst; y=1'b0; end S2: if (din == 1'b1) begin nst = S3; y=1'b0; end else begin nst = S0; y=1'b0; end S3: if (din == 1'b0) begin nst = S4; y=1'b0; end else begin nst = S1; y=1'b0; end S4: if (din == 1'b0) begin nst = S0; y=1'b1; end else begin nst = S1; y=1'b1; end default: nst = S0; endcase end always@(posedge clk) begin if (reset) cst <= S0; else cst <= nst; end endmodule MOORE WITH OVERLAP module morfsmolp(din, reset, clk, y); input din; input clk; input reset; output reg y; reg [2:0] cst, nst; parameter S0 = 3'b000, S1 = 3'b001, S2 = 3'b010, S3 = 3'b100, S4 = 3'b101; always @(cst or din) begin case (cst) S0: if (din == 1'b1) begin nst = S1; y=1'b0; end else nst = cst; S1: if (din == 1'b0) begin nst = S2; y=1'b0; end else begin nst = cst; y=1'b0; end S2: if (din == 1'b1) begin nst = S3; y=1'b0; end else begin nst = S0; y=1'b0; end S3: if (din == 1'b0) begin nst = S4; y=1'b0; end else begin nst = S1; y=1'b0; end S4: if (din == 1'b0) begin nst = S1; y=1'b1; end else begin nst = S3; y=1'b1; end default: nst = S0; endcase end always@(posedge clk) begin if (reset) cst <= S0; else cst <= nst; end endmodule Serial Adder using Mealy style........ module serial_add(a,b,cin,reset,clk,sum,nst); output reg sum; input a,b,cin; input clk; input reset; reg cst; output reg nst;/// carry out initial begin cst = cin; end /// state assignment parameter S0 = 1'b0, S1 = 1'b1; /// Synvhronous with clock.. always @(posedge clk) begin case (cst) S0 : begin sum=a^b; if(a&b) nst = S1; else nst = cst; end S0 : begin sum=~(a^b); if(~a&~b) nst = S0; else nst = cst; end default: nst = S0; endcase end /// reset facility always@(posedge clk) begin if (reset) cst <= S0; else cst <= nst; end endmodule A vending Machine Problem..................... module vending(T,F,reset,clk,y); output reg y; input T,F; input clk; input reset; wire [1:0] din; assign din = {T,F}; reg [2:0] cst, nst; parameter S0 = 2'b00, S1 = 2'b01, S2 = 2'b10, S3 = 2'b11; always @(posedge clk or din) begin case (cst) S0: if (din == 2'b00) begin nst = S0; y=1'b0; end else if (din == 2'b01) begin nst = S1; y=1'b0; end else if (din == 2'b10) begin nst = S2; y=1'b0; end S1: if (din == 2'b00) begin nst = S1; y=1'b0; end else if (din == 2'b01) begin nst = S2; y=1'b0; end else if (din == 2'b10) begin nst = S3; y=1'b1; end S2: if (din == 2'b00) begin nst = S2; y=1'b0; end else if (din == 2'b01) begin nst = S3; y=1'b1; end else if (din == 2'b10) begin nst = S2; y=1'b0; end S3: if (din == 2'b00) begin nst = cst; y=1'b0; end else if (din == 2'b01) begin nst = S1; y=1'b0; end else if (din == 2'b10) begin nst = S2; y=1'b0; end default: nst = S0; endcase end always@(posedge clk) begin if (reset) cst <= S0; else cst <= nst; end endmodule