module mux_df( input a,b,s, output y ); wire sbar; assign y = (a&sbar)|(s&b); assign sbar = ~s; endmodule module mux_bh( input a,b,s, output y ); reg y; wire s; always @( s or a or b ) begin if( s == 0) y = a; else y = b; end endmodule module mux_gl( input a,b,s, output y ); wire q1,q2,sbar; not n1( sbar,s); and a1( q1, sbar, a); and a2( q2, s, b); or o1( y, q1, q2); endmodule module mux_4_1( input a1,a2,a3,a4, input [1:0]s, output y ); wire t1,t2; mux_df m1(a1,a2,s[0],t1); mux_df m2(a3,a4,s[0],t2); mux_df m3(t1,t2,s[1],y); endmodule module mux_4_1_mix( input a1,a2,a3,a4, input [1:0] s, output y ); reg y; wire t1,t2; mux_df m1(a1,a2,s[0],t1); mux_gl m2(a3,a4,s[0],t2); always @( s[1] or t1 or t2 ) begin if( s[1] == 0) y = t1; else y = t2; end endmodule module mux_case( input a,b,s, output y ); reg y; always @(s or a or b) begin case(s) 0 : y = a; 1 : y = b; endcase end endmodule module mux_cs( input a,b,s, output y ); wire s; assign y = (s == 0)? a : b; endmodule //////Test benches///// module mux_tb; // Inputs reg a; reg b; reg s; // Outputs wire y; // Instantiate the Unit Under Test (UUT) mux_gl uut ( .a(a), .b(b), .s(s), .y(y) ); initial begin // Initialize Inputs a = 0; b = 0; s = 0; // Wait 100 ns for global reset to finish #100; a = 1; b = 0; s = 0; #20; a = 1; b = 0; s = 1; #20; a = 1; b = 1; s = 0; // Add stimulus here end endmodule ///////////////////////////////////// module mux_4_1_tb; // Inputs reg a1; reg a2; reg a3; reg a4; reg [1:0] s; // Outputs wire y; // Instantiate the Unit Under Test (UUT) mux_4_1 uut ( .a1(a1), .a2(a2), .a3(a3), .a4(a4), .s(s), .y(y) ); initial begin // Initialize Inputs a1 = 1; a2 = 1; a3 = 1; a4 = 0; s = 2'b00; // Wait 100 ns for global reset to finish #100; a1 = 1; a2 = 0; a3 = 0; a4 = 0; s = 2'b01; #20; a1 = 1; a2 = 0; a3 = 0; a4 = 1; s = 2'b10; #20; a1 = 0; a2 = 0; a3 = 0; a4 = 1; s = 2'b11; // Add stimulus here end endmodule