Half Adder

module ha(
  input a,b,
  output sum,co
    );
assign sum = a^b;
assign co = a&b;
endmodule

Full Adder using Half Adder

module fa(a,b,cin,sum,co);
input a,b,cin;
output sum,co; 
wire t1,t2,t3;
ha X1(a,b,t1,t2);
ha X2(cin,t1,sum,t4);
assign co = t2 | t4;
endmodule

Full Subtractor

module Subtractor(
  input a,b,bin,
  output d,bout
    );
wire a_bar;
assign a_bar = ~a;
assign d = a^b^bin;
assign bout = (b&bin)|(b&a_bar)|(a_bar&bin);
endmodule

Ripple Carry Adder

module RCA(a,b,cin,sum,co);
input [3:0] a,b;
input cin;
output [3:0] sum;
output co;
wire c1,c2,c3;
fa m1(a[0],b[0],cin,sum[0],c1);
fa m2(a[1],b[1],c1,sum[1],c2);
fa m3(a[2],b[2],c2,sum[2],c3);
fa m4(a[3],b[3],c3,sum[3],co);
endmodule

Controlled Adder/Subtractor

module Add_sub(a,b,ctrl,s,c);
input [3:0] a,b;
input ctrl;
output [3:0] s;
wire [3:0] b1;
output c;
wire c1,c2,c3;
assign b1[0] = ctrl ^ b[0];
assign b1[1] = ctrl ^ b[1];
assign b1[2] = ctrl ^ b[2];
assign b1[3] = ctrl ^ b[3];
fa m1(a[0],b1[0],ctrl,s[0],c1);
fa m2(a[1],b1[1],c1,s[1],c2);
fa m3(a[2],b1[2],c2,s[2],c3);
fa m4(a[3],b1[3],c3,s[3],c);
endmodule

Decoder

module decoder3_8(
   input [2:0] s,
	output [7:0] z
    );
reg [7:0] z;
always @ (s)
case(s)
3'b000 : z = 8'b10000000;
3'b001 : z = 8'b01000000;
3'b010 : z = 8'b00100000;
3'b011 : z = 8'b00010000;
3'b100 : z = 8'b00001000;
3'b101 : z = 8'b00000100;
3'b110 : z = 8'b00000010;
3'b111 : z = 8'b00000001;
default : z = 8'b0000000;
endcase	 
endmodule

BCD to Binary Coverter

module BCD2BIN(
   input [7:0] bcd,
   output [7:0] bin
    );
wire [3:0] t1,t2,t3,t4,sum1,sum2;
wire co1,co2;
parameter cin = 1'b0;
assign t1 = {bcd[5],bcd[3],bcd[2],bcd[1]};
assign t2 = {1'b0,bcd[4],bcd[5],bcd[4]};
RCA m1(t1,t2,cin,sum1,co1);////4-bit ripple carry adder
assign t3 = {1'b0,co1,sum1[3],sum1[2]};
assign t4 = {bcd[7],bcd[6],bcd[7],bcd[6]};
RCA m2(t3,t4,cin,sum2,co2);////4-bit ripple carry adder
assign bin = {co2,sum2,sum1[1:0],bcd[0]};
endmodule

Binary2Grey and Grey2Binary conversion

module B2G(
   input [3:0] b,
	output [3:0] g
    );
assign g[0] = b[0] ^ b[1];
assign g[1] = b[1] ^ b[2];
assign g[2] = b[2] ^ b[3];
assign g[3] = b[3];
endmodule

module G2B(
   input [3:0] g,
	output [3:0] b
    );
assign b[0] = g[0] ^ b[1];
assign b[1] = g[1] ^ b[2];
assign b[0] = g[2] ^ b[3];
assign b[0] = g[3];	 
endmodule

Parity Checker and Generator

module paritycheck_generate(
   input [3:0] a,
   output [4:0] odd_out,evn_out
    );
wire evn_parity,odd_parity;
///Parity Check
assign evn_parity = (a[0]^a[1]^a[2]^a[3]);

assign odd_parity = ~evn_parity;

////generate parity.....for ODD parity
assign {odd_out[4],odd_out[3:0]} = {odd_parity,a[3:0]};
////generate parity.....for EVEN parity
assign {evn_out[4],evn_out[3:0]} = {evn_parity,a[3:0]};
endmodule



Comparator................................................



module comp_1bit(a,b,lt,eq,gt);///////////////1-bit comparator

    input a,b;
    output lt,gt,eq;
	 wire abar,bbar;

assign abar = ~a;
assign bbar = ~b;
assign lt = abar & b;
assign gt = bbar & a;
assign eq = ~(lt|gt);
endmodule



module comparator4(A,B,LT1,GT1,EQ1,LT2,GT2,EQ2);///////////////4-bit comparator
    input [3:0] A,B;
    output LT2,GT2,EQ2;
	 input LT1,GT1,EQ1;
    

wire x30,x31,x32,x20,x21,x22,x10,x11,x12,x00,x01,x02;
wire x40,x41,x42,x50,x51,x52,x61,x62;
comp_1bit  c3(A[3],B[3],x30,x31,x32);
comp_1bit  c2(A[2],B[2],x20,x21,x22);
comp_1bit  c1(A[1],B[1],x10,x11,x12);
comp_1bit  c0(A[0],B[0],x00,x01,x02);

assign x40 = x31 & x20;
assign x41 = x31 & x21 & x10;
assign x42 = x31 & x21 & x11 & x00;

assign x50 = x31 & x22;
assign x51 = x31 & x21 & x12;
assign x52 = x31 & x21 & x11 & x02;
assign EQ = (x31 & x21 & x11 & x01);

assign EQ2 = EQ & EQ1;
assign x61 = EQ & LT1;
assign x62 = EQ & GT1;

assign LT2 = (x30 | x40 | x41 | x42) | x61;
assign GT2 = (x32 | x50 | x51 | x52) | x62;

endmodule



module comp16(a,b,lt1,gt1,eq1);///////////////16-bit comparator
    input [15:0] a,b;
    output lt1,gt1,eq1;
	 
	  parameter eq =1'b1;
	  parameter lt=1'b0;
	  parameter gt=1'b0;
	  
	 wire t11,t12,t13,t21,t22,t23,t31,t32,t33;
	 comparator4 c1(a[3:0],b[3:0],lt,gt,eq,t11,t12,t13);
	 comparator4 c2(a[7:4],b[7:4],t11,t12,t13,t21,t22,t23);
	 comparator4 c3(a[11:8],b[11:8],t21,t22,t23,t31,t32,t33);
	 comparator4 c4(a[15:12],b[15:12],t31,t32,t33,lt1,gt1,eq1);
	 endmodule


Scale Block..................


module CRSH1_18(a,b,s);
input [17:0] a;
output [17:0] b;
input s;
mux_df m1(a[17],a[17],s,b[17]);
mux_df m2(a[16],a[17],s,b[16]);
mux_df m3(a[15],a[16],s,b[15]);
mux_df m4(a[14],a[15],s,b[14]);
mux_df m5(a[13],a[14],s,b[13]);
mux_df m6(a[12],a[13],s,b[12]);
mux_df m7(a[11],a[12],s,b[11]);
mux_df m8(a[10],a[11],s,b[10]);
mux_df m9(a[9],a[10],s,b[9]);
mux_df m10(a[8],a[9],s,b[8]);
mux_df m11(a[7],a[8],s,b[7]);
mux_df m12(a[6],a[7],s,b[6]);
mux_df m13(a[5],a[6],s,b[5]);
mux_df m14(a[4],a[5],s,b[4]);
mux_df m15(a[3],a[4],s,b[3]);
mux_df m16(a[2],a[3],s,b[2]);
mux_df m17(a[1],a[2],s,b[1]);
mux_df m18(a[0],a[1],s,b[0]);
endmodule



module CRSH2_18(a,b,s);
input [17:0] a;
output [17:0] b;
input s;
mux_df m1(a[17],a[17],s,b[17]);
mux_df m2(a[16],a[17],s,b[16]);
mux_df m3(a[15],a[17],s,b[15]);
mux_df m4(a[14],a[16],s,b[14]);
mux_df m5(a[13],a[15],s,b[13]);
mux_df m6(a[12],a[14],s,b[12]);
mux_df m7(a[11],a[13],s,b[11]);
mux_df m8(a[10],a[12],s,b[10]);
mux_df m9(a[9],a[11],s,b[9]);
mux_df m10(a[8],a[10],s,b[8]);
mux_df m11(a[7],a[9],s,b[7]);
mux_df m12(a[6],a[8],s,b[6]);
mux_df m13(a[5],a[7],s,b[5]);
mux_df m14(a[4],a[6],s,b[4]);
mux_df m15(a[3],a[5],s,b[3]);
mux_df m16(a[2],a[4],s,b[2]);
mux_df m17(a[1],a[3],s,b[1]);
mux_df m18(a[0],a[2],s,b[0]);
endmodule



module CRSH4_18(a,b,s);
input [17:0] a;
output [17:0] b;
input s;
mux_df m1(a[17],a[17],s,b[17]);
mux_df m2(a[16],a[17],s,b[16]);
mux_df m3(a[15],a[17],s,b[15]);
mux_df m4(a[14],a[17],s,b[14]);
mux_df m5(a[13],a[17],s,b[13]);
mux_df m6(a[12],a[16],s,b[12]);
mux_df m7(a[11],a[15],s,b[11]);
mux_df m8(a[10],a[14],s,b[10]);
mux_df m9(a[9],a[13],s,b[9]);
mux_df m10(a[8],a[12],s,b[8]);
mux_df m11(a[7],a[11],s,b[7]);
mux_df m12(a[6],a[10],s,b[6]);
mux_df m13(a[5],a[9],s,b[5]);
mux_df m14(a[4],a[8],s,b[4]);
mux_df m15(a[3],a[7],s,b[3]);
mux_df m16(a[2],a[6],s,b[2]);
mux_df m17(a[1],a[5],s,b[1]);
mux_df m18(a[0],a[4],s,b[0]);
endmodule



module CRSH8_18(a,b,s);
input [17:0] a;
output [17:0] b;
input s;
mux_df m1(a[17],a[17],s,b[17]);
mux_df m2(a[16],a[17],s,b[16]);
mux_df m3(a[15],a[17],s,b[15]);
mux_df m4(a[14],a[17],s,b[14]);
mux_df m5(a[13],a[17],s,b[13]);
mux_df m6(a[12],a[17],s,b[12]);
mux_df m7(a[11],a[17],s,b[11]);
mux_df m8(a[10],a[17],s,b[10]);
mux_df m9(a[9],a[17],s,b[9]);
mux_df m10(a[8],a[16],s,b[8]);
mux_df m11(a[7],a[15],s,b[7]);
mux_df m12(a[6],a[14],s,b[6]);
mux_df m13(a[5],a[13],s,b[5]);
mux_df m14(a[4],a[12],s,b[4]);
mux_df m15(a[3],a[11],s,b[3]);
mux_df m16(a[2],a[10],s,b[2]);
mux_df m17(a[1],a[9],s,b[1]);
mux_df m18(a[0],a[8],s,b[0]);
endmodule



module VRSH_18(a,b,s);
input [17:0] a;
output [17:0]b;
input [3:0] s;
wire [17:0] t1,t2,t3;
CRSH1_18 m1(a,t1,s[0]);
CRSH2_18 m2(t1,t2,s[1]);
CRSH4_18 m3(t2,t3,s[2]);
CRSH8_18 m4(t3,b,s[3]);
endmodule


Division by Constant 3...................


module rsh2(a,b);
    input [17:0] a;
    output [17:0] b;
assign {b[17:15],b[14:0]}= {a[17],a[17],a[17],a [16:2]};
endmodule



module rsh4(a,b);
    input [17:0] a;
    output [17:0] b;
assign {b[17:13],b[12:0]}= {a[17],a[17],a[17],a[17],a[17],a[16:4]};
endmodule



module rsh6(a,b);
    input [17:0] a;
    output [17:0] b;    
assign {b[17:11],b[10:0]}= {a[17],a[17],a[17],a[17],a[17],a[17],a[17],a[16:6]};
endmodule



module rsh8(a,b);
    input [17:0] a;
    output [17:0] b;   
assign {b[17:9],b[8:0]}= {a[17],a[17],a[17],a[17],a[17],a[17],a[17],a[17],a[17],a[16:8]};
endmodule




module adder_18(a,b,cin,sum,co);
input [17:0] a,b;
input cin;
output [17:0] sum;
output co;
wire c1,c2,c3,c4,c5,c6,c7,c8,c9,c10,c11,c12,c13,c14,c15,c16,c17;
fa m1(a[0],b[0],cin,sum[0],c1);
fa m2(a[1],b[1],c1,sum[1],c2);
fa m3(a[2],b[2],c2,sum[2],c3);
fa m4(a[3],b[3],c3,sum[3],c4);
fa m5(a[4],b[4],c4,sum[4],c5);
fa m6(a[5],b[5],c5,sum[5],c6);
fa m7(a[6],b[6],c6,sum[6],c7);
fa m8(a[7],b[7],c7,sum[7],c8);
fa m9(a[8],b[8],c8,sum[8],c9);
fa m10(a[9],b[9],c9,sum[9],c10);
fa m11(a[10],b[10],c10,sum[10],c11);
fa m12(a[11],b[11],c11,sum[11],c12);
fa m13(a[12],b[12],c12,sum[12],c13);
fa m14(a[13],b[13],c13,sum[13],c14);
fa m15(a[14],b[14],c14,sum[14],c15);
fa m16(a[15],b[15],c15,sum[15],c16);
fa m17(a[16],b[16],c16,sum[16],c17);
fa m18(a[17],b[17],c17,sum[17],c0);
endmodule




module scale3(a,b);//////////////Scale block..........
input [17:0] a;
output [17:0] b;
wire [17:0] t1,t2,t3,t4,t5,t6;
wire co1,co2,co3;
parameter cin = 1'b0;
rsh2 m1(a,t1);
rsh4 m2(a,t2);
rsh6 m3(a,t3);
rsh8 m4(a,t4);
adder_18 m5(t1,t2,cin,t5,co1);
adder_18 m6(t3,t4,cin,t6,co2);
adder_18 m7(t5,t6,cin,b,co3);
endmodule